5 results about "Transferring (function)" patented technology

The invention discloses a data processing method, computer equipment, a readable storage medium and a program product, and relates to the technical field of data processing.The data processing method comprises the steps that initial data is acquired; obtaining a conversion configuration rule; querying a generation logic for generating target data by using the initial data in the conversion configuration rule; and calling a transfer function corresponding to the generation logic from the transfer function set as a target function, and executing the target function on the initial data to obtain target data. The technical problem of data processing mode solidification caused by hard codes is solved, and the technical effect of improving data processing flexibility so as to improve data processing performance is achieved.

The application discloses a PID anti-integral saturation method, system, device and medium for an Ovation control system, and the method comprises the following steps: a TRANSFER function block is arranged between the output end of a PID controller and an actuator; a real-time limit value signal is acquired, and the real-time limit value signal comprises an upper limit signal value and a lower limit signal value; the output signal of the PID controller is compared with the real-time limit value signal, and the TRANSFER function block is triggered according to the comparison result; and the output value of the TRANSFER function block is reversely transmitted to the PID controller through a tracking line by using a preset configuration tracking function, so as to reset the internal operation result of the PID controller. By adding the TRANSFER function block at the output end of the PID controller and introducing the real-time limit value signal which dynamically changes with the working condition, the technical limitation that the internal limiting parameter of the PID module of the Ovation system cannot be introduced and cannot follow in real time is solved.

A test system is provided which includes an actuator that actuates a test piece, a virtual model that operates in association with the test piece, a controller that controls the actuator, a computing device that computes the virtual model, and an inverse transfer function correcting unit that corrects a signal from the virtual model with a proper inverse transfer function that is determined based on a transfer function of a system including communication units between the test piece and the actuator and between the actuator and the controller and a communication unit between the computing device and the controller. The controller controls the actuator based on the signal corrected by the inverse transfer function correcting unit.

This network system comprises: a network failure information management unit that manages information about failure locations of a first ETB and a second ETB; a VLAN setting unit; a routing setting unit; a transfer function unit; and a frame rewriting function unit that rewrites the destination of a frame determined by the transfer function unit to be a frame addressed to the failure locations. When a failure occurs in the second ETB, the VLAN setting unit sets a bypass VLAN between an ECN of the configuration of a preceding stage of a location where the failure occurs, an ECN of the configuration of a subsequent stage of the location where the failure occurs, and a first ETB between the configuration of the preceding stage and the configuration of the subsequent stage. The routing setting unit: rewrites, to a routing entry addressed to the first ETBN, a routing entry addressed to an ETBN of the configuration of the subsequent stage of the location where the failure occurs; routes, according to the rewritten routing entry, a frame of which the destination has been rewritten by a frame rewriting function unit; and transmits the frame via the bypass VLAN.

A system is disclosed. The system includes at least one physical memory device to store compensation logic and one or more processors coupled with the at least one physical memory device to execute the compensation logic to generate first and second sets of transfer functions to compensate for a gap region, wherein each set of transfer functions is generated for a corresponding group of overlapping pel forming elements based on ink deposition functions associated with the corresponding group and a joint target response; wherein the gap region is located between overlapping pel forming elements of the corresponding groups.