44results about How to "Layer can be damaged" patented technology

A method of forming a silicon nitride film comprises: forming a silicon nitride film by applying first gas containing silicon and nitrogen and second gas containing nitrogen and hydrogen to catalyst heated in a reduced pressure atmosphere. A method of manufacturing a semiconductor device comprising the steps of: forming a silicon nitride film by the method as claimed in claim 1 on a substrate having the semiconductor layer, a gate insulation film selectively provided on a principal surface of the semiconductor layer, and a gate electrode provided on the gate insulation film; and removing the silicon nitride film on the semiconductor layer and the gate electrode and leaving a sidewall comprising the silicon nitride film on a side surface of the gate insulation film and the gate electrode by etching the silicon nitride film in a direction generally normal to the principal surface of the semiconductor layer. A method of manufacturing a semiconductor device comprising the steps of: forming a silicon nitride film by the method as claimed in claim 1 on a substrate including a semiconductor layer; forming an interlayer insulation layer on the silicon nitride film; forming a layer having an opening on the interlayer insulation layer; and etching the interlayer insulation layer via the opening in a condition where an etching rate for the silicon nitride film is greater than an etching rate for the interlayer insulation layer.

A display substrate and a method of manufacturing the same. The display substrate includes a substrate including an active area and an inactive area, an organic light-emitting diode (OLED) unit disposed on the active area of the substrate, and a transmittance measurement pattern unit disposed on the inactive area of the substrate. The transmittance measurement pattern unit includes a deposition assistant layer pattern disposed on the substrate.

The present invention is directed towards a method of manufacturing a semiconductor memory device arranged of a cross point memory array having memory elements provided between upper and lower electrodes for storage of data. The present invention comprises a lower electrode lines forming step of planarizing each of the lower electrode lines and insulating layers provided on both sides of the lower electrode line so as to be substantially uniform in the height thus for patterning the lower electrode lines, a memory element layer depositing step of depositing on the lower electrode lines a memory element layer for the memory elements, and an annealing step of annealing with heat treatment either between the lower electrode lines forming step and the memory element layer depositing step or after the memory element layer depositing step so that any damages caused by the polishing of the surface of the lower electrode lines can be eliminated.

Disclosed herein are an organic light-emitting device having a structure formed by the sequential deposition of a substrate, a first electrode, at least two organic layers and a second electrode, in which the organic layers include a light-emitting layer, and one of the organic layers, which is in contact with the second electrode, is a buffer layer comprising a compound represented by the following formula 1, as well as a fabrication method thereof:

wherein R¹ to R⁶ have the same meanings as defined in the specification. The buffer layer makes it possible to minimize or prevent damage to the organic layer, which can occur when forming the second electrode on the organic layer.

A method is provide for manufacturing a lithium anode and to a lithium anode for a lithium cell and/or a lithium battery. In order to improve the service life, performance capability and safety of a lithium cell and/or a lithium battery equipped with the lithium anode, the lithium anode includes a surface-structured current conductor and/or a surface-structured protective layer having at least one surface section circumscribed by a raised surface section, the surface structuring/structurings forming at least one cavity, and the at least one cavity being, in particular electrochemically, filled with anode active material. Also provided are a lithium cell and a lithium battery equipped with a lithium anode.

A nitride semiconductor layer-containing structure having a configuration in which: the structure includes a laminated structure based on at least two nitride semiconductor layers; the structure includes between the two nitride semiconductor layers in the laminated structure a plurality of voids surrounded by the faces of the walls inclusive of the inner walls of the recessed portions of the asperity pattern formed on the nitride semiconductor layer that is the lower layer of the two nitride semiconductor layers; and crystallinity defect-containing portions to suppress the lateral growth of the nitride semiconductor layer are formed on at least part of the inner walls of the recessed portions to form the voids.

To eliminate generation of a damaged layer caused by dry etching of a contact layer, occurring in a manufacturing process of a ridge waveguide type semiconductor laser, and to improve reliability and yield thereof, a method is provided involving forming a spacer layer and a damage receptor layer on the contact layer, making the two layer absorb damage caused by dry etching a passivation film in an upper portion of the ridge waveguide structure, and thereafter removing the damaged layer by the dry etching, by selective removal by wet etching.

There is provided a method for processing a semiconductor wafer subjected to a chamfering process, a lapping process, an etching process, and a mirror-polishing process, wherein acid etching is performed after alkaline etching as the etching process, and the acid etching is performed with an acid etchant composed of hydrofluoric acid, nitric acid, phosphoric acid, and water, a method for processing a semiconductor wafer subjected to a chamfering process, a surface grinding process, an etching process, and a mirror-polishing process, wherein the etching process is performed as described above, and a method for processing a semiconductor wafer subjected to a flattening process, an etching process, and a mirror-polishing process, wherein the etching process is performed as described above, a back surface polishing process is performed after the acid etching as the mirror-polishing process, and then a front surface polishing process is performed. According to this, there can be provided a method for processing a semiconductor wafer to have good flatness, good surface roughness, and good condition on a back surface thereof.

Laser treatment of tissue, particularly the tissues in or around the nasal and oral cavities, are described herein. One method for reducing the size of the tissue being treated is to apply laser energy to the underlying tissue. One instrument may be used to deliver laser energy and to optionally provide an infusion or injection of a fluid directly into the tissue as well as optionally provide for ultrasound energy application as well. One or more optical fibers which may extend through needles inserted into the tissue may be utilized to deliver the laser energy.

A film formation system and a film formation method are disclosed. The film formation method includes the following steps performed in the film formation system that includes a container containing liquid, a water draining means for draining the liquid, a ring-shaped component installed in the container, and a carrying component installed in the liquid in the container for carrying at least a substrate: enabling the carrying component in the liquid and enabling the ring-shaped component to float on the liquid; when a film layer that is composed of nano-spheres is formed on the liquid, locating the film layer in a ring of the ring-shaped component; and removing the liquid, allowing the film layer to move downward in accordance with the ring-shaped component and be formed on the substrate, thereby preventing the nano-spheres from contacting an inner wall of the container and bursting, through the installation of the ring-shaped component.

Disclosed is an inspection method for inspecting the electrical characteristics of a device by bringing an inspecting probe into electrical contact with an inspection electrode. An insulating film formed on the surface of the inspection electrode is broken by utilizing a fritting phenomenon so as to bring the inspection electrode into electrical contact with the inspection electrode.

The invention is directed to reduction of a manufacturing cost and enhancement of a breakdown voltage of a PN junction portion abutting on a guard ring. An N− type semiconductor layer is formed on a front surface of a semiconductor substrate, and a P type semiconductor layer is formed thereon. An insulation film is formed on the P type semiconductor layer. Then, a plurality of grooves, i.e., a first groove, a second groove and a third groove are formed from the insulation film to the middle of the N− type semiconductor layer in the thickness direction thereof. The plurality of grooves is formed so that one of the two grooves next to each other among these, that is closer to an electronic device, i.e., to an anode electrode, is formed shallower than the other located on the outside of the one. Then, an insulating material is deposited in the first groove, the second groove and the third groove. The lamination body of the semiconductor substrate and the layers laminated thereon is then diced along dicing lines.

A high performance accelerator structure and method of production. The method includes precision machining the inner surfaces of a pair of half-cells that are maintained in an inert atmosphere and at a temperature of 100 K or less. The method includes removing thin layers of the inner surfaces of the half-cells after which the roughness of the inner surfaces in measured with a profilimeter. Additional thin layers are removed until the inner surfaces of the half-cell measure less than 2 nm root mean square (RMS) roughness over a 1 mm² area on the profilimeter. The two half-cells are welded together in an inert atmosphere to form an SRF cavity. The resultant SRF cavity includes a high accelerating gradient (E_acc) and a high quality factor (Q₀).

Provided is a method for manufacturing a field-effect transistor, the method including the steps of: forming a gate electrode on the surface of a substrate; forming a gate insulating layer on the gate electrode; forming a conductive film containing a conductor and a photosensitive organic component by a coating method on the gate insulating layer; exposing the conductive film from the rear surface side of the substrate with the gate electrode as a mask; developing the exposed conductive film to form a source electrode and a drain electrode; and forming a semiconductor layer by a coating method between the source electrode and the drain electrode. This method makes it possible to provide an FET, a semiconductor device, and an RFID which can be prepared by a simple process, and which have a high mobility, and have a gate electrode and source/drain electrodes aligned with a high degree of accuracy.

A method for manufacturing a silicon carbide substrate includes the steps of: preparing a seed substrate made of silicon carbide; etching a main surface of the seed substrate prepared; obtaining an ingot by growing a silicon carbide single crystal film on a crystal growth surface formed by etching the main surface of the seed substrate;

and obtaining a silicon carbide substrate by cutting the ingot. The step of etching the seed substrate includes: a first etching step of removing silicon atoms, which form the silicon carbide, from an etching region using chlorine gas, the etching region being a region including the main surface of the seed substrate; and a second etching step of removing carbon atoms, which form the silicon carbide, from the etching region from which the silicon atoms have been removed, using oxygen gas.

A low voltage power cable having an insulation layer with a density below 1100 kg/m³, which has a polyolefin having 0.002-4% mol of a compound that has polar groups and further having a compound that has hydrolysable silane groups and includes 0.0001-3% weight of a silanol condensation catalyst and a process of manufacturing such a cable.

An amount of a semiconductor substrate cut due to etching in the bottom of a contact hole formed by the SAC technique is reduced. Silicon oxide films are dry etched under the conditions of increasing the etching selective ratio of the silicon oxide films to an insulating film. Then, the conditions are changed to those increasing the etching selective ratio of the insulating film to the silicon oxide films and the insulating film is etched by a predetermined amount.

A grommet (20, 30) as part of a fastening element for a building envelope essentially comprises a head (21), a tip (22) and a sleeve (23) therebetween, wherein the head (21) is essentially constructed as an extensive washer (24), the central hole of which is adjoined by the tubular sleeve (23). The tip (22) narrows essentially in a conical or tapered manner to a smaller diameter. The grommet (20, 30) has a sensor arrangement (25), with at least one RFID transponder with antenna and a sensor operatively connected to the transponder.

The present disclosure discloses a method for manufacturing an array substrate comprising: forming a gate electrode on a substrate; forming a gate insulating layer on one side of the substrate facing the gate electrode, the gate insulating layer covering the gate electrode; depositing an indium gallium zinc tin oxide layer and an indium gallium zinc oxide layer on one side of the gate insulating layer away from the gate electrode; patterning the indium gallium zinc oxide layer and the indium gallium zinc tin oxide layer by a first yellow light process to form a protective layer and an active layer, the protective layer covering the active layer; depositing a metal layer on one side of the protective layer away from the active layer; and patterning the metal layer and the protective layer by a second yellow light process to form a source electrode, a drain electrode, and a separation region.