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112 results about "Dc field" patented technology

Tandem time of flight mass spectrometer and method of use

To provide comprehensive (i.e. rapid and sensitive) MS-MS analysis, the inventor employs a time-nested separation, using two time-of-flight (TOF) mass spectrometers. Parent ions are separated in a slow and long TOF1, operating at low ion energy (1 to l00eV), and fragment ions are mass analyzed in a fast and short TOF2, operating at much higher keV energy. Low energy fragmentation cell between TOF1 and TOF2 is tailored to accelerate fragmentation and dampening steps, mostly by shortening the cell and employing higher gas pressure. Since separation in TOF1 takes milliseconds and mass analysis in TOF2- microseconds, the invention provides comprehensive MS-MS analysis of multiple precursor ions per single ion pulse. Slow separation in TOF1 becomes possible with an introduction of novel TOF1 analyzers. The TOF-TOF could be implemented using a static TOF1, here described on the examples of spiratron, planar and cylindrical multi-pass separators with griddles spatial focusing ion mirrors. Higher performance is expected with the use of novel hybrid TOF 1 analyzers, combining radio frequency (RF) and quadratic DC fields. RF field retains low-energy ions within TOF 1 analyzer, while quadratic DC field improves resolution by compensate for large relative energy spread.
Owner:力可公司

Converter station DC field neutral bus lightning arrester charged analysis device and method

The present invention discloses a converter station DC field neutral bus lightning arrester charged analysis device. The device comprises a neutral bus lightning arrester, a DC neutral bus, an energy absorbing checking device, and a current nonuniformity analyzer. The DC neutral bus generates an operation over-voltage signal in DC system debugging. The primary side of the neutral bus lightning arrester is electrically connected to the DC neutral bus, and after the operation over-voltage signal passes by the neutral bus lightning arrester, the grounding side of the neutral bus lightning arrester generates a discharge current signal. The high voltage end of an impact voltage divider is electrically connected to the DC neutral bus, and the measuring end of the impact voltage divider generates a converted impact voltage signal. The device comprises a plurality of current sampling modules, the input ends of the current sampling modules are electrically connected to the grounded circuit of the neutral bus lightning arrester. The input end of a voltage sampling module is electrically connected to the measuring end of the impact voltage divider. The device has the advantage that energy absorption and discharge current unevenness of the lightning arrester can be monitored in real time during debugging and operation.
Owner:EXAMING & EXPERIMENTAL CENT OF ULTRAHIGH VOLTAGE POWER TRANSMISSION COMPANY CHINA SOUTHEN POWER GRID

Multi-process self-adaptive allocation multilayer super-large-scale integrated circuit field circuit coupling method

The invention discloses a multi-process self-adaptive allocation super-large-scale integrated circuit field-circuit coupling method, which perfectly realizes a rapid and accurate calculation target offield-circuit coupling of multi-layer super-large-scale integrated circuit direct-current field analysis by simplifying a three-dimensional problem into a two-dimensional problem and adopting a super-node technology. Field circuit coupling can be accurately and completely carried out on the multi-layer integrated circuit direct-current electric field, and the calculation speed of the multi-layerintegrated circuit and chip packaging direct-current electric field is increased. Meanwhile, coarse particle parallelism is achieved in the operation process, communication between processes and waiting time generated by synchronization are reduced to a great extent, meanwhile, due to the fact that a calculation task random dynamic allocation method is adopted, it is guaranteed that calculation models with unequal complexity are randomly and evenly distributed on all calculation nodes, and calculation efficiency is improved. And a hard disk read-write bottleneck caused by virtual memory accessdue to an overhigh peak memory is avoided.
Owner:北京智芯仿真科技有限公司

DC field layer simulation system, digital real-time emulation system and closed loop test system

The invention relates to a DC field layer simulation system, a digital real-time emulation system and a closed loop test system. The DC field layer simulation system comprises a field equipment model, a test and control device model, a communication model and a bus communication card and a collection card reading and writing module, wherein the field equipment model is used for simulating an AC/DC switch field, an AC/DC wave filter, a convertor transformer, an SER sequence event and an auxiliary signal in the field, the test and control device model can deliver operation commands, return the field equipment state and collect the analog variable, and the communication model is provided with a data collection card and a field bus communication card. The DC field layer simulation system simulates primary equipment and test and control devices in the field directly through the field equipment model and the test and control device model, reduces the building of the field physical test equipment environment, and can freely select devices to be tested in the simulation range, the problem of control incapability is avoided, the DC field layer simulation system is the system with actual and reliable test environment, and the expansion and the upgrading of the system are convenient.
Owner:XJ LIANHUA INT L ENVIRONMENTAL

Polymer coated long duration optical memory device and a method for the development thereof

The invention relates to a method for the preparation of a polymer coated long duration optical memory device having applications in ferroelectric liquid crystal materials, the said method comprising the steps of forming patterns of different shapes and configurations on a glass substrate coated with indium tin oxide by lithographic methods to obtain an effective electrode area of at least 5 mm2; depositing an antireflection coating on external surfaces of glass substrates followed by coating the patterned glass substrate with a polymer selected from the polyamide group of nylon 6/6 and nylon 6/9 in the thickness range of 900 Å-1100 Å; baking the coated substrate followed by hard rubbing of the polymer coated surface; coating one of the substrates with a spacer selected from photoresist having thickness in the range of 1 mum to 3 mum; inserting a ferroelectric liquid crystal material in the space between the coated glass substrates, followed by sealing the sandwiched glass substrates at the periphery; heating and cooling the sandwiched glass substrates; fixing a polariser and an analyser on non conducting surface of each of the respective glass plates, followed by application of electric field across the sandwiched substrates for achieving the stable memory action, by applying an AC and DC field across the device to obtain an optical memory device having a long duration of memory at least one year.
Owner:COUNCIL OF SCI & IND RES
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