The invention discloses a 3300V SiC DMOSFET low-conduction resistance device optimization method, and belongs to the technical field of low-conduction resistance device optimization, the 3300V SiC DMOSFET low-conduction resistance device optimization method comprises external parameter selection, cellular size design,
JFET region global
doping and
process design, the external parameter selection comprises selection of proper epitaxial thickness and
doping concentration of the device, the selection of the epitaxial thickness comprises selection of the epitaxial thickness and the
doping concentration of the device, and the selection of the epitaxial thickness comprises selection of the epitaxial thickness and the doping concentration of the device.
Simulation is based on Sensor TCAD
software, a half-
cell structure is adopted, the
simulation efficiency is improved, the area of an active region is 1.2 mm < 2 >, a breakdown condition criterion is a current abrupt change method, when the drain end current is larger than (Afault factor * 1 * 10 <-11 >), it is determined that the device is broken down, area factor is used for representing the
current density of the device in a three-dimensional plane, and the
current density of the device in the three-dimensional plane is used for representing the
current density of the device in the three-dimensional plane. According to the optimization method of the 3300V SiC DMOSFET low-conduction resistance device,
higher power density can be realized in smaller packaging, meanwhile, the heat dissipation requirement and the overall size of the
system are reduced, and in addition, the response speed and the stability of a circuit are improved due to the rapid switching characteristic and the low dynamic loss of the 3300V SiC DMOSFET low-conduction resistance device.