The invention provides an FPGA (
Field Programmable Gate Array) test method, which comprises the following steps that: a plurality of to-be-tested FPGA chips are in a serial test network, and a configuration
chip obtains data streams of the plurality of to-be-tested FPGA chips from flash and inputs the data streams into the serial test network; when any to-be-tested
FPGA chip in the serial test network is successfully configured, a pulse
signal is generated, and
test data transmission interfaces between the adjacent to-be-tested FPGA chips are controlled to be communicated for
data stream transmission; a configuration
control signal interface between the adjacent FPGA chips to be tested is controlled to be communicated, and the configuration
control signal interface is used for returning a pulse
signal; when any
FPGA chip to be tested is configured successfully, a pulse
signal is generated and transmitted back to the configuration
chip, and the configuration
chip retransmits the
data stream to the next
FPGA chip to be tested; and if the configuration of any FPGA chip to be tested fails, the configuration chip determines the position where the chip with the problem is configured and feeds back the position to the upper computer. The invention further provides an FPGA testing device.