The embodiment of the invention provides an IST module, a
chip, a
chip self-test method, a mainboard and
computer equipment, and the IST module comprises an IST state
machine which is used for generating a global reset
signal in an initialization stage of a
test program; in the execution process of the
test program, the test instruction is converted into a JTAG
signal for driving the TAP; the reset
control circuit is used for responding to an enabling state of a program continuing
signal in an initialization stage of a
test program, generating a local reset selection signal based on a global reset signal of an IST state
machine and outputting the local reset selection signal to the TAP so as to drive the TAP to reset a routing network and reserve the configuration of the TDR, so that the IST state
machine can reset the routing network in the execution process of the test program; driving the TAP to execute a
chip test based on the reserved TDR configuration; wherein the routing network is used for forming an access path of the target TDR so as to test the on-chip to-be-tested module corresponding to the target TDR through configuration of the target TDR. According to the embodiment of the invention, the
test scale of the IST mechanism of the chip can be improved, and the limitation of the IST mechanism is reduced.