This application discloses a method, medium, and device for half-
bus voltage balancing in a three-phase four-wire
inverter, relating to the field of
inverter technology. The method includes the following steps: when the half-
bus voltage difference is higher than a preset
voltage difference threshold, a compensation loop is activated to obtain the amplitude of a preset compensation
gain; the sign of the set compensation
gain is determined based on the
inverter's instantaneous active power; based on the compensation
gain and the half-
bus voltage difference, a zero-sequence compensation amount is calculated and superimposed on the zero-axis
voltage loop of the dq0 control frame; when the half-
bus voltage difference falls below the preset voltage difference threshold and remains for a preset time period, the compensation loop is exited. The medium and device are used to implement the above method. The beneficial effects of this application are: by adjusting the common-mode bias of the three-
phase modulation wave with the zero-sequence compensation amount, the dynamic adjustment of the upper and lower
capacitor connection time ratio is achieved. Its response speed is determined by the PWM
switching cycle, effectively suppressing rapidly accumulated charge imbalance within milliseconds.