The application discloses an embedded
voltage-stabilized heat-dissipation PCB structure with a thermoelectricity synergic regulation layer and a preparation method thereof. The structure comprises at least one PCB inner layer and a
chip power supply pad arranged on the inner layer, and a ring-shaped or C-shaped thermoelectric material pattern (ZT>0.5 at
room temperature) is embedded in a region corresponding to the
chip power supply pad directly below the inner layer. A first end of the thermoelectric material pattern is electrically connected to a power supply layer, and a second end is electrically connected to a grounding layer or a heat-dissipation through hole. The application utilizes the
temperature difference during the operation of a
chip to drive the thermoelectric material to generate a reverse
electromotive force to inhibit power supply
ripple, and simultaneously utilizes the Peltier effect to actively pump heat, so that the inner layer is integrated with
voltage stabilization and heat dissipation. The power supply
ripple can be reduced by 25% to 42% and the surface temperature of the chip can be reduced by 11 DEG C to 14 DEG C by using the PCB structure. The application directly integrates the thermoelectric function in the PCB inner layer, does not occupy the
surface layer area, and is suitable for the packaging substrate of high-
performance computing chips.