In a stacked 
chip configuration, and manufacturing methods thereof, the gap between a lower 
chip and an upper 
chip is filled completely using a relatively simple process that eliminates voids between the lower and upper chips and the 
cracking and 
delamination problems associated with voids. The present invention is applicable to both chip-level bonding and 
wafer-level bonding approaches. A 
photosensitive polymer layer is applied to a first chip, or 
wafer, prior to stacking the chips or stacking the wafers. The 
photosensitive polymer layer is partially cured, so that the 
photosensitive polymer layer is made to be structurally stable, while retaining its 
adhesive properties. The second chip, or 
wafer, is stacked, aligned, and bonded to the first chip, or wafer, and the photosensitive 
polymer layer is then cured to fully bond the first and second chips, or wafers. In this manner, adhesion between chips / wafers is greatly improved, while providing complete fill of the gap. In addition, 
mechanical reliability is improved and CTE mismatch is reduced, alleviating the problems associated with warping, 
cracking and 
delamination, and leading to an improvement in device yield and device reliability.