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7 results about "Si doped" patented technology

Low-temperature low-noise InP-based HEMT device structure

PendingCN121126818ALow noiseIsolation layer
The invention discloses a low-temperature and low-noise InP-based HEMT device structure which comprises a substrate layer, a first buffer layer, a second buffer layer, a first channel layer, a second channel layer, an isolation layer, a delta-Si doping layer, a barrier layer, an etching stop layer and a cap layer from bottom to top in sequence. Wherein the second buffer layer adopts gradient components, the component is InzAl1-zAs, z is 0.52-0.60, and the value of z is gradually increased from bottom to top in the thickness direction; the first channel layer adopts gradient components, the component is In < x > Ga < 1-x > As, and x is 0.60-0.80; and the x value is gradually increased from bottom to top in the thickness direction. By optimizing the structure of the device, the noise performance of the InP-based HEMT under the low-temperature condition is remarkably improved, and the low-temperature low-noise HEMT is of great significance to the design of a low-temperature low-noise amplifier.
Owner:DALIAN UNIV OF TECH

InAs / GaSb superlattice medium / long wave two-color infrared detector based on nBn structure

ActiveCN224069047UImprove absorption efficiencysuppress crosstalkSi dopedDark current
The utility model discloses an InAs / GaSb superlattice medium / long wave double-color infrared detector based on an nBn structure, which belongs to the technical field of optoelectronic devices and comprises a GaSb substrate, a non-doped GaSb buffer layer, a 14ML InAs / 7ML GaSb superlattice Si doped layer, a 14ML InAs / 7ML GaSb superlattice unintentional doped layer, a 4ML InAs / 7ML GaSb superlattice unintentional doped layer, a 8ML InAs / 6ML GaSb superlattice unintentional doped layer and a 8ML InAs / 6ML GaSb superlattice Si doped layer which are sequentially arranged from bottom to top. The medium / long wave absorption layers of 14ML InAs / 7ML GaSb superlattices and 8ML InAs / 6ML GaSb superlattices are combined, so that high absorption efficiency and low crosstalk of medium / long wave band response are realized, and low dark current and wide temperature range working capability are realized.
Owner:UNIV OF ELECTRONICS SCI & TECH OF CHINA

A multilayer topcon structure for perovskite / silicon tandem solar cell interface and a preparation method thereof

PendingCN122094298ADopantChemical physics
This invention discloses a multilayer TOPCon structure for the interface of perovskite / silicon tandem solar cells and its fabrication method. The multilayer TOPCon structure comprises, from bottom to top: a silicon substrate, multiple alternating layers of SiO2. x The tunneling layer and the poly-Si doped layer, wherein: SiO x The tunneling layer consists of 1 to 5 layers, with a single layer thickness of 0.8 to 1.2 nm, and SiO₂. x The total thickness of the tunneling layer is ≤3nm; and SiO x The tunneling layer is doped with nitrogen (N), with an N / O atomic ratio of 0.05–0.15; the number of poly-Si doped layers is related to the SiO₂ content. x The tunneling layer is consistent, and the total thickness of the poly-Si doped layer is 60~150 nm. P is used as the main dopant in the poly-Si doped layer, with an average concentration of activated P atoms of 1×10⁻⁶. 20 ~1×10 21 cm ‑3 Furthermore, the P doping concentration in the poly-Si doped layer increases in a gradient from the side closest to the silicon substrate to the side furthest from the silicon substrate. In this invention, the combination of multilayer TOPCon architecture and precise doping modification optimizes the carrier transport between the top and bottom cells, and the multilayer poly-Si structure effectively reduces total optical parasitics and improves the light capture efficiency of the tandem cell.
Owner:NANCHANG HANGKONG UNIVERSITY

Fin-HEMT (High Electron Mobility Transistor) with aluminum oxide gallium nitride gallium oxide heterojunction and manufacturing method of Fin-HEMT

The invention provides a Fin-HEMT (High Electron Mobility Transistor) with an aluminum oxide gallium nitride gallium oxide heterojunction and a manufacturing method of the Fin-HEMT. A buffer layer and a channel layer in the Fin-HEMT are sequentially arranged on a substrate; grooves are periodically etched in the channel layer along the gate width direction so as to construct and form a Fin structure; the doping layer and the barrier layer are sequentially arranged on the channel layer; wherein the channel layer is a beta-Ga2O3 layer, the doping layer is delta-Si doped beta-(AlxGa1-x) 2O3 as a delta modulation doping layer, an insertion channel layer is further arranged between the channel layer and the doping layer, the insertion channel layer is a GaN layer, the barrier layer is an unintentionally doped beta-(AlxGa1-x) 2O3 layer, and the barrier layer, the doping layer, the insertion channel layer and the channel layer are in contact to form a beta-(AlxGa1-x) 2O3 / GaN / Ga2O3 heterojunction structure. Two-dimensional electron gas is generated on one side, facing the doping layer, of the insertion channel layer; the grid electrode is arranged on the barrier layer. The Fin-HEMT is provided with a beta-(Al < x > Ga < 1-x >) < 2 > O < 3 > / GaN / Ga < 2 > O < 3 > heterojunction, 2DEG is generated on one side of an insertion channel layer at a heterojunction interface through deliberately doped delta-Si modulation, the channel mobility is improved, the on-resistance is reduced, and a certain improvement effect is achieved on the channel mobility by adopting a Fin structure.
Owner:HUBEI JIUFENGSHAN LAB

A high-efficiency light-emitting diode epitaxial wafer and preparation method thereof

The present invention provides a high-efficiency light-emitting diode epitaxial wafer and a preparation method thereof. The light-emitting diode epitaxial wafer comprises a substrate, and a buffer layer, a non-doped GaN layer, an N-type GaN layer, an N-type electron blocking layer, a multi-quantum well layer, an electron blocking layer and a P-type GaN layer sequentially deposited on the substrate; the N-type electron blocking layer comprises a SiN layer, an AlN layer, and a P-type GaN layer sequentially deposited on the N-type GaN layer. a Si 1‑a N layer and super lattice layer, the super lattice layer includes Si doped Al deposited alternately in a preset period b Ga 1‑b N layer and non-doped Al x In y Ga 1‑x‑y N layer. The present invention inserts an N-type electron blocking layer between the N-type GaN layer and the multi-quantum well layer to reduce the movement speed of electrons, effectively reducing the number of electrons in the N-type GaN layer rushing through the multi-quantum well layer to reach the P-type GaN layer and non-radiative recombination with holes, thereby improving the radiative recombination efficiency of electrons and holes in the quantum well layer.
Owner:JIANGXI ZHAO CHI SEMICON CO LTD

Ferroelectric film, ferroelectric memory unit, ferroelectric memory array and chip

The invention provides a ferroelectric film, a ferroelectric memory unit, a ferroelectric memory array and a chip. The ferroelectric film includes: a ferroelectric layer including 1% to 5% of an Al or Si doped ferroelectric material; or, 1% to 10% of a TiN or TaN doped ferroelectric material; or, comprises; wherein the value range of x is from 0.25 to 0.75, the value range of gamma is from 1.8 to 2.2, and the thickness of the ferroelectric layer is from 1 to 20 nanometers. The ferroelectric film material can be formed within the range of 1-5 nanometers, the element of the ferroelectric film material is a common and pollution-free material in the current silicon process, and the coercive field can be adjusted by adjusting the element doping concentration through the ferroelectric film with a high rectification ratio, so that the rectification ratio and the minimum leakage current critical voltage position are modulated, and the latent path leakage current in the FeTerRAM is reduced.
Owner:SHANGHAI SHENMING AOSI SEMICONDUCTOR TECHNOLOGY CO LTD

Fin-HEMT (High Electron Mobility Transistor) with aluminum oxide gallium oxide heterojunction and manufacturing method of Fin-HEMT

The invention provides a Fin-HEMT (High Electron Mobility Transistor) with an aluminum oxide gallium oxide heterojunction and a manufacturing method of the Fin-HEMT. The Fin-HEMT comprises a substrate, a buffer layer, a channel layer, a doping layer, a barrier layer and a grid electrode, the buffer layer and the channel layer are sequentially arranged on the substrate; grooves are periodically etched in the channel layer along the gate width direction so as to construct and form a Fin structure; the doping layer and the barrier layer are sequentially arranged on the channel layer so as to cover the whole wafer comprising the Fin structure; the channel layer is a beta-Ga2O3 layer, the doping layer is delta-Si doped beta-(AlxGa1-x) 2O3 as a delta modulation doping layer, the barrier layer is an unintentionally doped beta-(AlxGa1-x) 2O3 layer, the doping layer, the barrier layer and the channel layer are in contact to form a beta-(AlxGa1-x) 2O3 / beta-Ga2O3 heterojunction structure, and two-dimensional electron gas is generated on one side, facing the doping layer, in the channel layer; the grid electrode is arranged on the barrier layer. The Fin-HEMT is provided with a beta-(Al < x > Ga < 1-x >) < 2 > O < 3 > / beta-Ga < 2 > O < 3 > heterojunction structure, 2DEG is generated on one side of a beta-Ga < 2 > O < 3 > channel layer at a heterojunction interface through deliberately doped delta-Si modulation, the channel mobility is improved, the on-resistance is reduced, and a certain improvement effect is achieved on the channel mobility by adopting the Fin structure.
Owner:HUBEI JIUFENGSHAN LAB