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54results about How to "Reduce edge roughness" patented technology

Resist pattern-improving material and a method for preparing a resist pattern by using the same

The present invention provided an improvement to reduce an edge roughness during forming a small and fine pattern. Such and objective is to accomplish that after patterning a resist film, a coating film is formed on the resist film, so as to intermix the resist film material with the coating film material at the interface therebetween to reduce the edge roughness. There is provided a resist pattern-improving material, comprising: (a) a water-soluble or alkali-soluble composition, comprising: (i) a resin, and (ii) a crosslinking agent. Alternatively, The resist pattern-improving material, comprising (a) a water-soluble or alkali-soluble composition, comprising: (i) a resin, and (ii) a nonionic surfactant. According to the present invention, a pattern is prepared in the step, comprising: (a) forming a resist pattern; and (b) coating the resist pattern-improving material on the surface of the resist pattern. According to the present invention, the resist pattern-improving material is mixed with the resist pattern at the interface therebetween. The resist pattern may be formed by irradiating a ArF excimar laser light or a laser light having a wavelength shorter than that of the ArF excimar laser light. The pattern of the resist pattern-improving material includes a base resin which does not substantially transmit the ArF excimar laser light.
Owner:FUJITSU LTD

Calibration standard for critical dimension verification of sub-tenth micron integrated circuit technology

A critical dimension control wafer for calibrating process control scanning electron microscopes is described. The test wafer provides one or more test structures each consisting of an array of parallel trenches precision micro-machined in a metal plate. The trenches are formed, preferably in an aluminum / copper alloy plate, using focused ion beam milling. The micro-machined trenches have lower width roughness and lower edge roughness compared to similar patterns form in polysilicon by conventional photo lithographic methods. In addition, electron charging in the scanning electron microscope, which produces distorted images, is essentially eliminated. The dimensions of the trenches and the metal lines between them have dimensions comparable to those of polysilicon lines used in sub-tenth micron integrated circuit process technology control wafer. The control wafers are calibrated using a calibrated laboratory grade scanning electron microscope. Once calibrated, the control wafers may be stock-piled for subsequent routine use as a high precision dimensional reference, in particular for calibrating and monitoring the stability of process line scanning electron microscopes.
Owner:TAIWAN SEMICON MFG CO LTD
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