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70 results about "Nanomanufacturing" patented technology

Nanomanufacturing is both the production of nanoscaled materials, which can be powders or fluids, and the manufacturing of parts "bottom up" from nanoscaled materials or "top down" in smallest steps for high precision, used in several technologies such as laser ablation, etching and others. Nanomanufacturing differs from molecular manufacturing, which is the manufacture of complex, nanoscale structures by means of nonbiological mechanosynthesis (and subsequent assembly).

Method of forming monolithic cmos-mems hybrid integrated, packaged structures

A method of forming Monolithic CMOS-MEMS hybrid integrated, packaged structures includes the steps of providing: providing a semiconductor substrate with pre-fabricated cmos circuits on the front side and a polished back-side with through substrate conductive vias; forming at least one opening in the polished backside of the semiconductor substrate by appropriately protecting the front-side; applying at least one filler material in the at least one opening on the semiconductor substrate; positioning at least one prefabricated mems, nems or cmos chip on the filler material, the chip including a front face and a bare back face with the prefabricated mems/nems chips containing mechanical and dielectric layers; applying at least one planarization layer overlying the substrate, filler material and the chip; forming at least one via opening on a portion of the planarization layer interfacing pads on the chip and the through substrate conductive vias; applying at least one metallization layer overlying the planarization layer on the substrate and the chip connecting the through substrate conductive vias to the at least one chip; applying at least one second insulating layer overlying the metallization layer; performing at least one micro/nano fabrication etching step to release the mechanical layer on the prefabricated mems/nems chips; positioning protective cap to package the integrated device over the mems/nems device area on the pre-fabricated chips.
Owner:AMF NANO

Method for measuring clearance in proximity nanometer lithography

The invention discloses a method for measuring clearance in proximity nanometer lithography and mainly aims at the controlling of the clearance of a masking silicon wafer in nanometer manufacturing technology, such as nano-imprint, wave zone plate array imaging and the like. The basic process of the method can be simply explained in the picture 1 that: incident plane waves pass through a silicon wafer gratings and a mask grating and diffract for multiple times, wherein the two periods of the gratings are approximate and the two gratings are overlapped with a certain gap; two beams of lateral diffracted light from the two gratings interfere with each other and are superposed, and form Moire interference fringes of which the period is amplified relative to the conventional gratings on the surfaces of the silicon wafer grating; and the fringes are imaged on a CCD image detector through an objective lens with certain multiplying power. The change of the gap between the two gratings causes the change of optical path difference of the two beams and then causes the change of the movement or phases of the interference fringes so that the aim of measuring the gap is fulfilled; the more approximate the period is, the higher the sensitivity of the measurement is; and, at the same time, because the periods of the two gratings are approximate, the included angle between the lateral diffracted light is very small, the frequency of the interference fringes is very low (namely, the period is long), and the requirement on the numerical aperture of the objective lens is low. With the development of microfabrication technology, the machining accuracy of the grafting is higher and the method has great significance for gap measurement in proximity nanometer lithography and the related field.
Owner:INST OF OPTICS & ELECTRONICS - CHINESE ACAD OF SCI

Method of forming monolithic CMOS-MEMS hybrid integrated, packaged structures

A method of forming Monolithic CMOS-MEMS hybrid integrated, packaged structures includes the steps of providing: providing a semiconductor substrate with pre-fabricated cmos circuits on the front side and a polished back-side with through substrate conductive vias; forming at least one opening in the polished backside of the semiconductor substrate by appropriately protecting the front-side; applying at least one filler material in the at least one opening on the semiconductor substrate; positioning at least one prefabricated mems, nems or cmos chip on the filler material, the chip including a front face and a bare back face with the prefabricated mems / nems chips containing mechanical and dielectric layers; applying at least one planarization layer overlying the substrate, filler material and the chip; forming at least one via opening on a portion of the planarization layer interfacing pads on the chip and the through substrate conductive vias; applying at least one metallization layer overlying the planarization layer on the substrate and the chip connecting the through substrate conductive vias to the at least one chip; applying at least one second insulating layer overlying the metallization layer; performing at least one micro / nano fabrication etching step to release the mechanical layer on the prefabricated mems / nems chips; positioning protective cap to package the integrated device over the mems / nems device area on the pre-fabricated chips.
Owner:AMF NANO
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