The invention belongs to the technical field of packaging integrated chips, and relates to a six-surface packaging method for a 3D integrated
chip. The method comprises the following steps: mounting a plurality of 3D integrated chips on a first
wafer substrate; carrying out five-
surface plastic package on the plurality of 3D integrated chips,
thinning the plastic
package of one side, far away from the first
wafer substrate, of the plastic
package wafer, and exposing the chips;
etching a micro-channel and manifold channel structure on the back surface of the exposed
chip; bonding a second wafer substrate on one side of the exposed
chip of the plastic package wafer; performing pressed film encapsulation on one side of the plastic package wafer, which is provided with the external
interconnection structure, and partially removing encapsulation on the external
interconnection structure by adopting an ultrafast
laser technology to
expose the external
interconnection structure; a heat dissipation cover plate is bonded and sealed on one side, provided with the micro-channel and manifold channel structure, of the chip; and preparing a
solder ball connected with the external interconnection structure on the plastic package wafer. The external interconnection structure of the integrated chip is simplified, and the packaging
process efficiency and reliability are improved.