31results about How to "Reduce the probability of electric leakage" patented technology

The invention discloses a capacitor structure, a semiconductor device and a capacitor structure preparation method. A supporting structure is arranged on the outer side wall of a lower electrode of acolumnar structure; the supporting structure comprises a top supporting structure for supporting the upper area of the lower electrode; the top supporting structure at least comprises a first supporting layer and a second supporting layer made of a material different from that of the first supporting layer. The lower surface of the first supporting layer is arranged to be in contact with the uppersurface of the second supporting layer, the contact interface of the first supporting layer and the second supporting layer is lower than the top of the lower electrode, and the upper surface of thefirst supporting layer is higher than the top of the lower electrode; a capacitor dielectric layer covering the lower electrode and the support structure and an upper electrode covering the capacitordielectric layer are formed, so the electric leakage rate can be reduced while the extending height of the lower electrode in the vertical direction is met, the supporting structure at the position needing to be reserved is prevented from being damaged in the patterning process of the top supporting structure of the lower electrode, and the stability of the lower electrode and the performance of the capacitor structure can be effectively improved.

The invention relates to a light-emitting diode with gradually changed refractive index of a light-emitting layer. The refractive index of the light-emitting layer is gradually changed by arranging a protective layer outside the light-emitting layer of the light-emitting diode, wherein the refractive index of the material of the protective layer is between that of the material of the light-emitting layer and that of the packaging material of the light-emitting diode. The luminescent efficiency of the light-emitting diode can be improved and the leakage rate of the light-emitting diode can be reduced.

The invention provides a voltage detecting circuit, a battery power prompting system and a voltage detecting method. The voltage detecting circuit based on a digital circuit comprises a digital circuit, a conversion circuit and a comparison circuit. The digital circuit has a first output end, an input end and a second output end. The first output end outputs a digital signal. The input end of theconversion circuit is coupled to the first output end of the digital circuit. The first input end of the comparison circuit receives a voltage signal representative of the to-be-detected voltage. Thesecond input end of the comparison circuit is coupled to the output end of the conversion circuit. The output end of the comparison circuit is coupled to the input end of the digital circuit. The digital circuit obtains a to-be-detected voltage level based on the output signal of the comparison circuit, and provides a control signal at the second output end of the digital circuit, wherein the control signal is generated based on the to-be-detected voltage level. According to the voltage detecting circuit, the battery power prompting system and the voltage detecting method in the embodiment, the detection can be realized only by occupying two pins of the digital circuit, so that extension of other functions of the digital circuit is facilitated; meanwhile, the complexity, the volume and thecost of the system are reduced, so that the system integration is facilitated, thereby improving the reliability of a portable electric tool in a relatively poor working environment.

The invention provides a vertical epitaxial structure LED chip and a preparation method thereof, the vertical epitaxial structure LED chip comprises a substrate, an insertion layer, a conductive layer, a low-doped conductive layer and an LED structure layer which are sequentially arranged in a laminated manner, and the insertion layer is a hexagonal boron nitride layer; the conductive layer comprises a plurality of gallium nitride aluminum/gallium nitride heterojunction layers. The mutual acting force between the hexagonal boron nitride layered structures is small, and the damage of stripping to the upper epitaxial structure is small. And by utilizing the layered structure characteristic of the hexagonal boron nitride, the laser lift-off technology cannot damage the structure on the hexagonal boron nitride layer, so that the yield of the LED chip is improved. The gallium nitride aluminum/gallium nitride heterojunction structure can play a role similar to a chip DBR (Distributed Bragg Reflector) due to different materials. Moreover, through the design that the silicon-doped concentration of the gallium aluminum nitride/gallium nitride heterojunction layer is gradually reduced, the gallium aluminum nitride/gallium nitride heterojunction layer can be well matched with an electrode, and has good conductive and ohmic contact effects.

The invention provides a simple eutectic LED chip structure and a manufacturing method thereof. The LED chip structure comprises a P electrode, an N electrode, a Bragg reflection layer, a P welding layer, and an N welding layer, wherein the P electrode is arranged below the Bragg reflection layer and is connected with the P welding layer through a first through hole penetrating through the Bragg reflection layer; the N electrode is arranged below the Bragg reflection layer and is connected with the N welding layer through a second through hole penetrating through the Bragg reflection layer; and the electrode structures of the P welding layer and the N welding layer are respectively a Cr layer, an Al layer, (Ti layer/Pt layer)n, an Au layer and a Sn layer which are sequentially stacked on the Bragg reflection layer, and n represents the number of repetition times of the Ti layer and the Pt layer which are stacked. The manufacturing method comprises the steps of manufacturing a step structure, manufacturing a single wafer, manufacturing a P electrode and an N electrode, manufacturing a Bragg reflection layer, and manufacturing a P welding layer and an N welding layer. According to the invention, the eutectic difficulty is greatly reduced.

The invention discloses a flip LED chip structure with insulation protection and a manufacturing method thereof, and the flip LED chip structure with insulation protection is characterized in that an LED chip epitaxial structure is grown on a chip substrate, a chip current layering structure and N and P bonding pad regions are manufactured, a compact insulating film is deposited on a sliced chip unit to serve as an insulating protection layer, and the insulating protection layer is formed on the chip substrate. And the insulating protection layer wraps and covers the chip structure except the N and P bonding pad areas, and comprises the front surface, the back surface and the side surface of the chip unit. The surrounding type insulation protection LED chip structure is adopted, the compact insulation film is deposited on the sliced chip unit to serve as the insulation protection layer, the electric leakage rate can be reduced, the yield of the chip can be improved, meanwhile, the light emitting efficiency is enhanced, the reliability of long-term use of a device is enhanced, and water vapor erosion is restrained.

The invention provides a filter tube and a super-soft soil solidifying device provided with the same. The filter tube is a TPU wired hose. The TPU wired hose comprises a tube body made of TPU plasticmaterials, and a steel wire wound in the tube body spirally. The filter tube of the super-soft soil solidifying device has very high ring stiffness and cannot be vacuumized to be flat during vacuumizing generally, and the problem of flattening of a horizontal water drainage channel is free of worry.

The invention discloses a manufacturing method for a high reliability VDMOS power device, and belongs to the technical field of integrated circuit design. The method includes growing an epitaxial silicon layer on a silicon substrate; depositing a shielding layer on the epitaxial silicon layer; designing a photomask of a P-well pattern, performing corrosion, and removing the redundant shielding layer; manufacturing a P well; depositing a silicon dioxide layer on the surface to perform corrosion to form two side triangular structures; manufacturing a contact end and a source end; and taking outthe contact end and the source end. Through the increasing of the shielding layer and the silicon dioxide layer of a power VDMOS device, the fixing of the effective dimension of a channel can be realized, so that the probability of the occurrence of electric leakage can be reduced; and the method is simple in processing technology and strong in controllability, and has strong maneuverability.

The invention discloses an electric heating faucet with a waterproof function. The electric heating faucet comprises a shell, a base arranged in the shell and internally provided with a heating cavity, an electric heating body arranged in the heating cavity, a side barrel welded to one side of the shell in a vertical manner in the radial direction, a water inlet channel communicated with the heating cavity and used for supplying water to the heating cavity, a water outlet channel communicated with the heating cavity and enabling the water in the heating cavity to flow out through the water outlet channel and a switching valve arranged in the side barrel and used for controlling on and off of the water inlet channel, wherein the heating cavity is formed in the base, and two first sealing rings are arranged between the shell and the base at intervals. According to the electric heating faucet with the waterproof function, the two first sealing rings are arranged between the shell and the base, so that the water cannot enter a gap between the shell and the base, the electric leakage probability of the faucet is reduced, and the condition that a damp environment is provided for rusting and corrosion after the water enters the position between the shell and the base is effectively prevented.

The invention discloses solid-state capacitance negative carbon foil. The solid-state capacitance negative carbon foil comprises a corrosion aluminum foil layer, wherein the corrosion aluminum foil layer is provided with upper and lower rough surfaces, upper and lower metal transition layers with high affinity to aluminum and graphite are plated on the upper and lower rough surfaces of the corrosion aluminum foil layer respectively through a magnetron sputtering manner, and upper and lower graphite layers are plated on outer surfaces of the upper and lower metal transition layers respectively through a magnetron sputtering manner. A manufacture method of the solid-state capacitance negative carbon foil includes the following steps of taking corrosion aluminum foil with the upper and lower rough surfaces, subsequently performing sputtering plating of the upper and lower metal transition layers with high affinity to aluminum and graphite on the upper and lower surfaces of the corrosion aluminum foil by means of a magnetron sputtering manner under a vacuum condition, and finally performing sputtering plating of a graphite layer on the outer surfaces of the upper and lower metal transition layers through a magnetron sputtering manner again. According to the solid-state capacitance negative carbon foil, the graphite layer is not prone to fall off, and the solid-state capacitance negative carbon foil has the advantages of being long in service life, large in electric capacity, low in leakage rate, small in impedance, and the like.

The invention provides a semiconductor structure and a formation method thereof. The formation method comprises the following steps: providing a substrate; carrying out plasma sulfurizing treatment onthe substrate; and after the plasma sulfurizing treatment is carried out on the substrate, forming a high-K dielectric layer on the substrate. Electrical properties of the semiconductor structure formed by adopting the formation method of the invention are improved.

The invention discloses an epitaxial structure provided with a Bragg reflector, a preparation method thereof and an LED chip, the epitaxial structure comprises a GaN composite layer, the Bragg reflector, an N-GaN layer, a stress release layer, a quantum well layer, a P-AlGaN layer and a P-GaN layer which are arranged in sequence, the Bragg reflector is composed of a plurality of periods of AlN layers/GaN layers, and the stress release layer is composed of a plurality of periods of N layers/GaN layers. The growth temperature of the AlN layer and the growth temperature of the GaN layer in the Bragg reflector are the same and range from 900 DEG C to 1200 DEG C. The epitaxial structure is high in luminous efficiency and good in antistatic performance, and surface cracks of the Bragg reflector are few.