108 results about "Nanomesh" patented technology

A new method is disclosed for the exfoliation of hexagonal boron nitride into mono- and few-layered nanosheets (or nanoplatelets, nanomesh, nanoribbons). The method does not necessarily require high temperature or vacuum, but uses commercially available h-BN powders (or those derived from these materials, bulk crystals) and only requires wet chemical processing. The method is facile, cost efficient, and scalable. The resultant exfoliated h-BN is dispersible in an organic solvent or water thus amenable for solution processing for unique microelectronic or composite applications.

This invention relates to the preparations of noble metal catalysts, i.e., platinum and platinum alloys, on suitable supports with nanonetwork structures and high catalytic efficiencies. A compact structure of a monolayer or a few layers is formed by self-assembly of organic polymer, e.g., polystyrene (PS), nanospheres or inorganic, i.e., silicon dioxide (SiO2), nanospheres on a support surface. In the void spaces of such a compact arrangement, catalyst is formed by filling with catalyst metal ion-containing aqueous solution and reduced by chemical reduction, or formed by vacuum sputtering. When using organic polymer nanospheres as the starting or structure-directing material, the polymer particles are removed by burning at a high temperature and the catalyst having a nanonetwork structure is obtained. In the case of using silicon dioxide nanospheres as the starting material, silicon dioxide particles are dissolved with hydrofluoric acid solution and evaporated away leading to formation of a similar nanonetwork structure made of catalyst. The catalysts prepared by these methods possess characteristics of robust in structure, uniform in hole size and high in catalytic surface area. Their main applications include uses as catalysts in direct methanol and proton exchange membrane fuel cells, as well as in chemical reactors, fuel reformers, catalytic converters, etc.

Methods, apparatuses, and systems are disclosed for flexible thermal ground planes. A flexible thermal ground plane may include a support member. The flexible thermal ground plane may include an evaporator region or multiple evaporator regions configured to couple with the support member. The flexible thermal ground plane may include a condenser region or multiple condenser regions configured to couple with the support member. The evaporator and condenser region may include a microwicking structure. The evaporator and condenser region may include a nanowicking structure coupled with the micro-wicking structure, where the nanowicking structure includes nanorods. The evaporator and condenser region may include a nanomesh coupled with the nanorods and / or the microwicking structure. Some embodiments may include a micromesh coupled with the nanorods and / or the microwicking structure.

A method, an apparatus and an article of manufacture for attracting charged nanoparticles using a graphene nanomesh. The method includes creating a graphene nanomesh by generating multiple holes in graphene, wherein each of the multiple holes is of a size appropriate to a targeted charged nanoparticle, selectively passivating the multiple holes of the graphene nanomesh to form a charged ring in the graphene nanomesh by treating the graphene nanomesh with chemistry yielding a trap with an opposite charge to that of the targeted nanoparticle, and electrostatically attracting the target charged nanoparticle to the oppositely charged ring to facilitate docking of the charged nanoparticle to the graphene nanomesh.

In one aspect, a method of fabricating an electronic device includes the following steps. An alternating series of device and sacrificial layers are formed in a stack on an SOI wafer. Nanowire bars are etched into the device / sacrificial layers such that each of the device layers in a first portion of the stack and each of the device layers in a second portion of the stack has a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region. The sacrificial layers are removed from between the nanowire bars. A conformal gate dielectric layer is selectively formed surrounding the nanowire channels in the first portion of the stack which serve as a channel region of a nanomesh FET transistor. Gates are formed surrounding the nanowire channels in the first and second portions of the stack.

The present invention relates to a method of forming copper nanowires with a metallic coating. In a preferred embodiment, the metallic coating is copper. Due to the metal coating, the nanowires become magnetically guidable and chemically stable. As such, the nanowires can be used to form nanomesh. Further, the nanowire and nanomesh of the present invention can be used as transparent electrodes that are used in TV, PC, touch-control, and solar industries.