32results about How to "Lower ohmic contact" patented technology

An apparatus and processes for large scale inline manufacturing of CdTe photovoltaic modules in which all steps, including rapid substrate heating, deposition of CdS, deposition of CdTe, CdCl₂ treatment, and ohmic contact formation, are performed within a single vacuum boundary at modest vacuum pressures. A p+ ohmic contact region is formed by subliming a metal salt onto the CdTe layer. A back electrode is formed by way of a low cost spray process, and module scribing is performed by means of abrasive blasting or mechanical brushing through a mask. The vacuum process apparatus facilitates selective heating of substrates and films, exposure of substrates and films to vapor with minimal vapor leakage, deposition of thin films onto a substrate, and stripping thin films from a substrate. A substrate transport apparatus permits the movement of substrates into and out of vacuum during the thin film deposition processes, while preventing the collection of coatings on the substrate transport apparatus itself.

A semiconductor device according to the present invention includes a silicon carbide semiconductor substrate having a silicon carbide semiconductor layer; a p-type impurity region provided in the silicon carbide semiconductor layer and including a p-type impurity; a p-type ohmic electrode electrically connected to the p-type impurity region; an n-type impurity region provided in the silicon carbide semiconductor layer adjacent to the p-type impurity region, and including an n-type impurity; and an n-type ohmic electrode electrically connected to the n-type impurity region. The p-type ohmic electrode contains an alloy of nickel, aluminum, silicon and carbon, and the n-type ohmic electrode contains an alloy of titanium, silicon and carbon.

The invention discloses a method for manufacturing a silicon solar cell. In the process of manufacturing a PN junction on a silicon wafer, a selective diffusion technology method is adopted, i,e. laser is utilized to heat a position, on which a positive electrode intends to be manufactured, on the surface of the silicon wafer; and under the action of heating, phosphorus in a phosphorus source uniformly adhered on the surface diffuses towards the inner of the silicon wafer, thus a heavy doping zone with smaller sheet resistance is formed at the position on which the positive electrode intends to be manufactured to effectively reduce the sheet resistance of the silicon solar cell, thereby not only being beneficial for increasing the open-circuit voltage of the silicon solar cell; the increase of the open-circuit voltage effectively improves the conversion efficiency of the silicon solar cell, reduces ohmic contact of a metal electrode and the silicon solar cell, thereby reducing the series resistance of the silicon solar cell, and being capable of meeting the purpose of industrialized production better.

A transparent conductive oxide contact layer to enhance the spectral output of a light emitting device and a methodology for its deposition. The transparent conductive oxide deposited on the light emitting device so as to have a columnar structure. The transparent conductive oxide contact layer may be preferably ZnO doped with a conductive element. Light emitting phosphors may also be deposited within the transparent conductive oxide contact layer.

A nitride semiconductor LED comprises a substrate; an n-type nitride semiconductor layer formed on the substrate; an active layer formed on a predetermined region of the n-type nitride semiconductor layer; a p-type nitride semiconductor layer formed on the active layer; a p-electrode formed on the p-type nitride semiconductor layer; and an n-electrode formed on the n-type nitride semiconductor layer in which the active layer is not formed. The p-electrode and n-electrode are formed to have such a multilayer structure that an ohmic contact layer, a compound layer containing aluminum or silver, and a degradation preventing layer are sequentially laminated.

The object is to provide a method for the fabrication of a semiconductor device having undergone an anneal treatment for the purpose of forming such ohmic contact as enables decrease of ohmic contact resistance and being provided on the (000-1) plane of silicon carbide with an insulating film and provide the semiconductor device. The method for the fabrication of a silicon carbide semiconductor device includes the steps of performing thermal oxidation on the (000-1) plane of a silicon carbide semiconductor in a gas containing at least oxygen and moisture, thereby forming an insulating film in such a manner as to contact the (000-1) plane of the silicon carbide semiconductor, removing part of the insulating film, thereby forming an opening part therein, depositing contact metal on at least part of the opening part, and performing a heat treatment, thereby forming a reaction layer of the contact metal and silicon carbide, wherein the heat treatment is implemented in a mixed gas of an inert gas and hydrogen.

The invention provides a chip scale package light-emitting apparatus having recessed design and a manufacturing method thereof. The chip scale package light-emitting apparatus includes a flip chip type LED chip and a cladding structure. The cladding structure covers the LED chip, and has a bottom surface warps upwardly to for a recessed shape. The invention also provides a manufacturing method for manufacturing the light-emitting apparatus. The apparatus and the method can avoid or improve poor quality of welding points between the light-emitting apparatus and a substrate which is often caused by greater gap between an electrode group of the LED chip and a welding pad of the substrate due to expansion of the cladding structure upon being heated in reflow soldering or eutectic bonding. Therefore, the apparatus and the method can secure the electrode group to the substrate. With excellent welding quality, failure of electrical connection of the light-emitting apparatus can be avoided, the thermal resistance between the light-emitting apparatus and the substrate can be lowered, temperature at the binding point can be lowered when the light-emitting apparatus operates, and light-emitting efficiency and reliability can be improved.

The invention discloses a method for welding a silicon wafer and a molybdenum piece in a semiconductor device. The method comprises the following steps that firstly, a first silver layer is arranged on the molybdenum piece; secondly, a second silver layer is arranged on the anode electrode of the silicon wafer; thirdly, a third silver layer is arranged between the first silver layer and the second silver layer; fourthly, the silicon wafer and the molybdenum piece are welded together by welding the first silver layer, the second silver layer and the third silver layer. According to the method, the technology is simple, the yield and the welding strength are high, the voidage of welding layers is low, the deformation is small, and the performance of the product can be greatly improved. The invention further relates to an application of the silicon wafer/molybdenum piece manufactured through the method.

An image sensor array includes a substrate and a plurality of pixels. Each pixel includes a single photon avalanche detector (SPAD), a quench device coupled to a respective SPAD and configured to quench an avalanche current, and time measurement circuitry configured to measure a time-of-flight of a photon. The SPAD has a trench coupled to the substrate and having a lattice mismatch with the substrate, and a substantially defect-free region coupled to the trench and configured to generate the avalanche current when the photon is detected in the defect-free region, wherein the trench and the defect-free region form an electrode. An imaging system includes an infrared laser configured to provide a pulse of light, and the image sensor array configured to receive the pulse from the infrared laser.

The invention discloses conductive paste for a positive electrode of a solar cell. The conductive paste is added with glass powder A with the mass fraction of 1.7-4% and glass powder B with the mass fraction of 0.1-1%, wherein the glass transition temperature of the glass powder A is 250-350 DEG C, and the glass transition temperature of the glass powder B is 350-450 DEG C. The invention also discloses a preparation method of the conductive silver paste and a solar cell front electrode prepared by applying the conductive silver paste to a silicon wafer cut by a diamond wire. According to the conductive paste for the positive electrode of the solar cell, the glass powder A and the glass powder B with different glass softening temperatures are used as inorganic adhesives of the conductive paste; the bonding performance of the conductive slurry on the surface of a silicon wafer is improved, the degree of etching the surface of the silicon wafer by molten glass powder in the conductive slurry is improved, doping is improved, the ohmic contact of a metal-semiconductor contact layer on the surface of the silicon wafer is reduced, and the unit consumption ratio of a positive electrode ofa solar cell is reduced by 5-10%.

The present invention provides a manufacture method of an oxide semiconductor TFT substrate, and the method comprises steps of: 1, forming a gate (3) and a first heavily doped transparent conducting thin film layer (2) on a substrate (1); 2, deposing a gate isolation layer (4); 3, forming an island shaped oxide semiconductor layer (5); 4, forming an island shaped photoresistor layer (6); 5, forming a source/a drain (8), and a second, a third heavily doped transparent conducting thin film layer (7, 9), and the source/the drain (8) contact the two side parts (53) of the island shaped oxide semiconductor layer (5) via the second heavily doped transparent conducting thin film layer (7) to establish electrical connections; 6, deposing and patterning a protecting layer (10); 7, deposing and patterning a pixel electrode layer (11) which contacts the source/the drain (8) via the third heavily doped transparent conducting thin film layer (9) to establish electrical connections; 8, implementing anneal process.

An oxide semiconductor TFT substrate includes a substrate, a gate and a first heavily doped transparent conducting layer formed on a substrate and covered by a gate isolation layer. An island shaped oxide semiconductor layer and an island shaped etching stopper layer are sequentially formed on the gate isolation layer with two side parts of the oxide semiconductor layer exposed outside the etching stopper layer. A source and a drain are formed on the two side parts of the oxide semiconductor layer to be in electrical connection therewith with a heavily doped transparent conducting layer therebetween. A protecting layer is formed on the source and the drain and is formed with a via. A pixel electrode extends through the via to electrically connect to the source and the drain with a heavily doped transparent conducting layer interposed therebetween and in direct contact therewith.

Systems and methods that provide a barrier for protection of active layers associated with a vertical multi junction (VMJ) photovoltaic cell. Buffer zone(s) in form of an inactive layer(s) arrangement safe guard the active layers against induced stress or strain resulting from external forces/thermal factors (e.g., welding). The buffer zone can be in form of a rim on a surface of an end layer of a cell unit, to act as a protective boundary for such active layer, and to further partially frame the VMJ cell for ease of handling and transportation.

The invention discloses a silicon-based stress covariant substrate and a preparation method thereof, and a vertical structure gallium nitride LED using the silicon-based stress covariant substrate anda preparation method thereof. The silicon-based stress covariant substrate comprises a double-sided polished silicon single crystal substrate; a thin zirconium nitride conductive reflective stress covariant layer which is formed on the double-sided polished silicon single crystal substrate, and the thickness of the thin zirconium nitride conductive reflective stress covariant layer is 50nm-350nm;and a thin gallium nitride single crystal film template layer which is formed on the thin zirconium nitride conductive reflective stress covariant layer, and the thickness of the thin gallium nitridesingle crystal film template layer is not less than that of the thin zirconium nitride conductive reflective stress covariant layer. The silicon-based stress covariant substrate can overcome and relieve the problem of large mismatch stress during high-quality preparation and growth of GaN materials and LED devices.

The invention provides an LED chip capable of improving external quantum efficiency. The LED chip comprises a DBR layer, a substrate, a buffer layer, a first semiconductor layer, an active layer, a second semiconductor layer, a transparent conductive layer, an N type electrode and a P type electrode, wherein the N type electrode and the P type electrode are both aluminum-based reflection electrodes, and the aluminum metal layer of the P type electrode is in direct contact with the transparent conductive layer to improve the reflectivity of a reflection electrode and a semiconductor interface.The invention further provides a preparation method of the LED chip capable of improving the external quantum efficiency. The method comprises the following steps: growing a complete LED structure epitaxial wafer on a substrate, and etching to form a semiconductor structure with a step inclined plane; manufacturing a current blocking layer and a transparent conductive layer comprising an AZO layer; preparing a P type electrode, an N type electrode and a passivation layer, and performing back plating of a DBR layer; and preparing the wafer into the LED chip device. According to the invention, the aluminum-based reflecting electrode is adopted, and the insertion layer metal between the P type electrode and the transparent conductive layer is canceled, so that the luminous efficiency of the LED chip is improved, and the external quantum efficiency of the LED chip is improved.

The invention discloses a four-section back electrode back electric field screen printing plate, which comprises a back electrode of a five-main-grid four-section structure and a back electric field of the five-main-grid four-section structure, and the back electric field correspondingly overprints and covers the back electrode. The back electrode corresponds to the front main grid in position andis divided into four sections by the electrode, and the length of each section is 11 +/-3mm. The length of the back electrode is reduced; the width of the back electrode is increased, and the overlapping area of the back electrode and the back electric field is increased; on the basis of not increasing the consumption of the back silver, the silver-aluminum overlapping area of a junction area isincreased, the conductivity of the back electrode is better improved, ohmic contact of the back silver and the back aluminum is greatly improved, Rs is greatly reduced, longitudinal silicon exposure design is added for a short plate and the back electrode at the welding starting position of an assembly series welding machine, assembly pseudo soldering corresponding to the assembly can be improved,and the assembly tension and the fragment rate are improved.