1results about How to "Reduce sample preparation costs" patented technology

This application relates to the field of semiconductor technology and provides a method for preparing and analyzing high-power bare chip failure analysis samples. The method includes: fixing the back surface of the high-power bare chip under test to the patch area of ​​a carrier substrate; wire bonding the functional electrode area on the amorphous back surface of the chip to the lead pads of the carrier substrate; preparing a polymer encapsulation layer on the amorphous back surface to obtain a molded high-power bare chip; peeling the molded high-power bare chip from the patch area of ​​the carrier substrate; grinding, fine polishing, and thinning the back surface to obtain the target failure analysis sample; powering the target failure analysis sample by connecting the lead pads outside the back surface area; observing the back surface area of ​​the target failure analysis sample to determine the failure location. This application not only avoids high-power bare chips being broken down or burned by high voltage and high current in failure analysis scenarios, but also significantly improves the sample preparation efficiency and quality of high-power bare chip failure samples.