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82 results about "Solid phase crystallization" patented technology

Preparation method for zeolite-immobilized photocatalyst

The invention relates to preparation technology of a photocatalyst and aims to provide a preparation method for a zeolite-immobilized photocatalyst. The preparation method comprises the following steps: dispersing a photocatalyst in deionized water, then adding a silicon source and carrying out a reaction under stirring; taking a reaction product out for washing and drying, subjecting the dried reaction product to mixing with a template and an aluminum source and then carrying out grinding; filling a reaction vessel with a mixture obtained in the previous step and carrying out solid-phase crystallization so as to produce a carrier with a zeolite structure; and washing and drying the carrier and then carrying out sintering in a muffle furnace to remove the template so as to obtain the zeolite-immobilized photocatalyst. According to the method, the usage amount of the template is low; due to improvement of the preparation method, the photocatalyst can be perfectly enveloped in a zeolite monocrystal, and the content of the photocatalyst is controllable; raw materials used in the method is low, and preparation process is simple; and in subsequent application, the utilization rate of the photocatalyst is high, the yield of the zeolite-immobilized photocatalyst is high, and the zeolite-immobilized photocatalyst has high organic pollutant degradation rate and exerts good protection effect on natural substances.
Owner:ZHEJIANG UNIV

TFT substrate manufacturing method and TFT substrate

The invention provides a TFT substrate manufacturing method and a TFT substrate. The method employs the SPC (Solid Phase Crystallization) technology to prepare an LTPS (Low Temperature Poly-Silicon) layer, and can reduce costs and form crystalline grains with better uniformity compared with the excimer laser crystallization technology; meanwhile, a bigrid structure is introduced, thereby enhancing the control of grids to channels, increasing the on state current of a film transistor, reducing off state current, inhibiting warping effects, reducing a threshold voltage and a subthreshold gradient, and improving the driving capability of the film transistor; besides, top grids can cover light, and reduce channel photoinduced electric leakage. The invention provides the TFT substrate, the LTPS layer of which is prepared through the SPC technology, and the TFT is low in production costs; in addition, the TFT substrate is provided with the bigrid structure, allowing the film transistor to have better electric property and strong driving capability, and not easy to generate channel photoinduced electric leakage.
Owner:TCL CHINA STAR OPTOELECTRONICS TECH CO LTD

Low-temperature growth method of silicon quantum dots for solar battery

The invention relates to a low-temperature growth method of silicon quantum dots for a solar battery, which belongs to the technical field of silicon quantum dot material. The method comprises the following steps: alternately growing a silicon compound dielectric layer of the stoichiometric proportion and a silicon compound layer containing Si which is several nanometers thick in stoichiometric ratio on a silicon wafer or a quartz sheet or a glass sheet or a stainless steel sheet or high-temperature resistant polymer substrate material at the temperature lower than 450 DEG C by using the plasma chemical vapour deposition (PCVD) technology; carrying out post annealing treatment at the temperature lower than or equal to 550 DEG C by using the rapid photo-thermal annealing technology, so that the residual Si in the silicon compound layer containing Si generates diffusion transfer and solid phase crystallization to form the Si quantum dots, wherein the formed Si quantum dots are arranged in a layered mode, the size of each Si quantum dot is controlled by the thickness of the originally-grown silicon compound layer containing Si, and the density of each Si quantum dot is determined by the content of Si in the original SiN<x> layer containing Si. The invention has the advantages of low depositing temperature, quick speed and good technology controllability and repeatability, thus the uniformity of the grown silicon quantum dot material is good; and the invention is favorable for integrated manufacture and cost reduction of devices.
Owner:YUNNAN NORMAL UNIV

Multi-cycle rapid thermal annealing method of amorphous silicon film

The invention relates to a multi-cycle rapid thermal annealing method of an amorphous silicon film, belonging to the technical field of preparation technology of a polycrystalline silicon film. The method comprises the following steps of: depositing an amorphous silicon film on a common glass slide substrate by a vapor deposition method; performing rapid thermal treatment, wherein the heating rate is about 150-200 DEG C/s; after the film sample is heated to 640 DEG C from room temperature, keeping the temperature for a while, and cooling naturally; when the film temperature reaches room temperature, performing next cycle; and after rapid thermal annealing is carried out several times, crystallizing the amorphous silicon film. Through the method, a polycrystalline film with crystallization rate being about 71.9% can be prepared. Compared with the traditional solid-phase crystallization technology of an amorphous silicon film, the method provided by the invention reduces requirements on the substrate, shortens the treatment time and has the characteristics of simple preparation technology, little pollution, low cost and the like. The polycrystalline silicon film prepared by using the method provided by the invention can be applied to the manufacture field of microelectronics such as thin-film transistors and solar cells.
Owner:SHANGHAI UNIV

TFT substrate manufacturing method and TFT substrate

The invention provides a TFT substrate manufacturing method and a TFT substrate. The TFT substrate manufacturing method comprises the steps of depositing a buffer layer and an amorphous silicon germanium layer on a substrate; implanting doped ions at the upper portion of the amorphous silicon germanium layer so as to form a doped amorphous silicon germanium layer; employing a rapid thermal annealing process for crystallization processing on the doped amorphous silicon germanium layer and the un-doped amorphous silicon germanium layer. Because the crystallization process begins from the doped amorphous silicon germanium layer and the crystallization temperature of the doped amorphous silicon germanium layer is low, the crystallization process can be carried out at a low temperature; because the un-doped amorphous silicon germanium layer in contact with the doped amorphous silicon germanium layer can be crystallized continuously at the low temperature, the doped polysilicon germanium layer and the un-doped polysilicon germanium layer can be obtained; compared with prior art, like existing solid phase crystallization, the crystallization process of the present invention can be carried out at a lower temperature, and the crystallization time can be shortened; the crystallization effect can be improved; and larger and more uniform crystal grains can be obtained.
Owner:SHENZHEN CHINA STAR OPTOELECTRONICS TECH CO LTD

LED (Light-Emitting Diode) wafer modularized packaging process

InactiveCN102969433AEfficient packaging manufacturing processHigh speedSolid-state devicesSemiconductor devices for light sourcesIndium tin oxideChipset
The invention relates to an LED (Light-Emitting Diode) wafer modularized packaging process which particularly comprises the following steps of: firstly connecting single or multiple LED chips in upright or reverse structures in series and in parallel to form an LED chipset; and then mounting the LED chipset to a substrate or a support frame by using LED chip mounting equipment. After the single or multiple LED chips are connected in series and in parallel to form the LED chipset, a metal wire and a metal film wire or a transparent indium tin oxide wire are adopted as outgoing wires, wherein the upright LED chips are welded on the outgoing wires by using gold wires and ball welding spots, and the reverse LED chips are welded on the outgoing wires by using eutectic welding spots; and the LED chip mounting equipment is a solid-phase crystallization machine or a chip mounting machine. The LED wafer modularized packaging process disclosed by the invention ensures that the packaging and manufacturing processes of the LED chips are more efficient; and compared with the traditional LED packaging mode, the LED wafer modularized packaging process disclosed by the invention adopts the simplest chip mounting manufacturing mode of a chip mounting resistor, thereby greatly increasing the speed of LED packaging and manufacturing, enhancing the productivity and reducing the cost.
Owner:SHANGHAI DANGOO ELECTRONICS TARDING

Method for producing small-spacing LED full-color display array

The invention discloses a method for producing a small-spacing LED full-color display array. The method for producing the small-spacing LED full-color display array comprises the steps of producing metal electrodes on the peripheral edge of the front side of a transparent panel, wherein the metal electrodes include row metal electrodes and column metal electrodes; directly arranging front-mounted LED chips in a middle area of the front side of the transparent panel in a solid phase crystallization mode to form an array; connecting P-electrodes of each row of chips in a wire bonding mode and connecting the P-electrodes with the row metal electrodes on the edge of the transparent panel; connecting N-electrodes of each column of chips in a wire bonding mode and connecting the N-electrodes with the column metal electrodes on the edge of the transparent panel; conducting sealing adhesive protection on the front side of the transparent panel to form a packaging adhesive and manufacturing a reflecting mirror on the surface of the packaging adhesive. Due to the fact that an electric insulation layer is not needed in the method, the yield of the small-spacing LED full-color display array is improved, and defective pixels (unlighted chips) are decreased. Process steps for producing the small-spacing LED full-color display array are greatly simplified, production efficiency is improved, and cost is reduced.
Owner:INST OF SEMICONDUCTORS - CHINESE ACAD OF SCI
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