134results about How to "Good lattice matching" patented technology

Novel articles and methods to fabricate the same resulting in flexible, {100}<100> or 45°-rotated {100}<100> oriented, semiconductor-based, electronic devices are disclosed. Potential applications of resulting articles are in areas of photovoltaic devices, flat-panel displays, thermophotovoltaic devices, ferroelectric devices, light emitting diode devices, computer hard disc drive devices, magnetoresistance based devices, photoluminescence based devices, non-volatile memory devices, dielectric devices, thermoelectric devices and quantum dot laser devices.

Novel articles and methods to fabricate the same resulting in flexible, oriented, semiconductor-based, electronic devices on {110}<100> textured substrates are disclosed. Potential applications of resulting articles are in areas of photovoltaic devices, flat-panel displays, thermophotovoltaic devices, ferroelectric devices, light emitting diode devices, computer hard disc drive devices, magnetoresistance based devices, photoluminescence based devices, non-volatile memory devices, dielectric devices, thermoelectric devices and quantum dot laser devices.

The present invention solves the problem of conventional group-III nitride semiconductor LED in that, since the LED driving current is supplied only from a pad electrode serving also as an ohmic electrode, the driving current cannot diffuse over a wide range of the light-emitting region and a group-III nitride semiconductor LED having high light emission intensity cannot be successfully provided. A group-III nitride semiconductor LED having high light emission intensity, which is fabricated using a stacked layer structure obtained by providing a surface ohmic electrode, a window layer including an electrically conducting transparent oxide crystal layer and a pad electrode on an electrically conducting substrate through a boron phosphide (BP)-based buffer layer to allow the driving current to diffuse over a wide range of the light-emitting region is provided.

A hard bias structure for biasing a free layer in a MR element within a read head is comprised of a composite hard bias layer having a Co_78.6Cr_5.2Pt_16.2/Co₆₅Cr₁₅Pt₂₀ configuration. The upper Co₆₅Cr₁₅Pt₂₀ layer has a larger Hc value and a thickness about 2 to 10 times greater than that of the Co_78.6Cr_5.2Pt_16.2 layer. The hard bias structure may also include a BCC underlayer such as FeCoMo which enhances the magnetic moment of the hard bias structure. Optionally, the thickness of the Co_78.6Cr_5.2Pt_16.2 layer is zero and the Co₆₅Cr₁₅Pt₂₀ layer is formed on the BCC underlayer. The present invention also encompasses a laminated hard bias structure. The Mrt value for the hard bias structure may be optimized by adjusting the thicknesses of the BCC underlayer and CoCrPt layers. As a result, a larger process window is realized and lower asymmetry output during a read operation is achieved.

The invention provides ultraviolet (UV) light-emitting diodes (LEDs). The UV LEDs can comprise abase layer including p-type SiC or p-type AlGaN, an active layer, and an n-AlGaN layer, wherein the active layer is disposed between the base layer and the n-AlGaN layer. In some embodiments, the absorption losses in p-SiC can be decreased or prevented by incorporating a conductive AlGaN Distributed Bragg Reflector (DBR) between the p-type SiC layer and the active layer. In some embodiments, the n-AlGaN layer can be textured to increase the extraction efficiency (EE). In some embodiments, the external quantum efficiency of the LEDs can be 20-30% or more.

The invention relates to nitride semiconductor component having a Group III nitride layer structure which is deposited on a substrate having a Group IV substrate surface made of a Group IV substrate material with a cubical crystal structure. The Group IV substrate surface has an elementary cell with C2 symmetry, but not with a higher rotational symmetry than C2 symmetry, when any surface reconstruction is ignored. The Group III nitride layer structure has a seeding layer of ternary or quaternary Al_1-x-yIn_xGa_yN, where 0≦x, y<1 and x+y≦1, immediately adjacent to the Group IV substrate surface. High-quality monocrystalline growth is achieved as a result. The advantage of the invention consists in the high level of crystal quality that can be achieved, in the growth of c-, a- and m-plane GaN and above all in the ease with which the silicon substrate can be wholly or partially removed, since this is easier to do in a wet chemical process than on (111)-oriented substrates.

The invention provides a method for manufacturing a gallium nitride-based semiconductor device having low-density crystalline defects and high-quality crystalinity. In the manufacturing method according to the invention, first, a gallium oxide substrate is prepared. Then, a surface of the gallium oxide substrate is modified into a nitride via physical or chemical pretreatment to form a surface nitride layer having Ga—N bonding. Finally, gallium nitride-based semiconductor layer is formed on the surface nitride layer.

The invention discloses a bismuth ferrite base film layer stacked structure capacitor and a preparation method thereof, wherein the capacitor comprises a bottom electrode, a substrate, a buffer layer, a ferroelectric film layer and a metal point electrode in sequence from the bottom to top; the buffer layer is a manganese-doped barium strontium titanate film, the chemical formula is Ba0.6Sr0.4Ti(1-x)MnxO3, x is the mole equivalent of element manganese, and x is equal to 0.005-0.05; and the ferroelectric film layer is a bismuth ferrite base film, the chemical formula is Bi(1-y)LnyFeO3, wherein Ln is one of lanthanide, y is the mole equivalent of lanthanide, and y is equal to 0.01-0.2. The preparation method is simple, and the obtained capacitor is a storage cell of a ferro-electric field effect transistor; and the capacitor overcomes the defects that the bismuth ferrite base film capacitor on ordinary silicon substrate has the defects of poor interface performance and high working voltage, and has good energy storage performance.

The invention discloses a nucleating agent for high-grade ductile iron and a preparation method of the nucleating agent. The nucleating agent for the high-grade ductile iron comprises the chemical components of 68-72% of Si, 3-5% of Ba, 1-3% of Ca, 0.15-0.6% of Sb and the balance Fe with the total weight of the nucleating agent for the high-grade ductile iron being 100%. By means of the nucleating agent for the high-grade ductile iron, the strength of the ductile iron can be increased, the elongation rate is increased, the hardness of the ductile iron is lowered, the cutting machinability is improved, and requirements for production and application are met.

The invention discloses a method for improving photoelectric conversion efficiency of solar cell panels and solves the technical problem that photoelectric conversion efficiency is affected due to imperfect processes of interface matching between a ZnO base transparent conductive film and a film in a photoelectric conversion area in the prior art. The technical scheme adopted in the invention is a method for improving photoelectric conversion efficiency of solar cell panels based on improved TCO film layers. The method comprises the step of depositing TCO film layers of ZnO base on a glass sheet, wherein the TCO film layers form a ZnO base composite film with 2-4 layers deposited on the glass sheet by ZnO base target with sputtering technology and doping concentrations of each layer of the composite film are distributed in gradient. The key of the invention is to design the TCO film layers in a multi-layer composite structure, control the doping concentrations of each layer reasonably to make the doping concentrations form a gradient, thus greatly enhancing light transmittance and conductivity of cell panels and effectively improving photoelectric conversion efficiency of solar cell panels.

The embodiment of the invention provides a thin film transistor, an amorphous silicon flat detecting substrate and a preparation method, which relate to the liquid crystal display technology. A source electrode and a drain electrode of the thin film transistor are made of conductors which are converted from materials of an amorphous metal oxide active layer by depositing insulating substances, the content of hydrogen ions of which is not less than a set value, thereby reducing the difference of the valence band level between the source electrode as well as the drain electrode and the active layer. The lattice matching performance is good, the influence of formed heterojunction or homojunction on a driving current signal is less, the electron flowing barrier is reduced, and the interface contact is improved, thereby reducing the influence of the difference of the valence band level between the source electrode as well as the drain electrode and the active layer on electrical properties of the thin film transistor.

A nitride semiconductor light emitting diode includes: an n-type clad layer; an active layer formed on the n-type clad layer; an electron blocking layer formed on the active layer, the electron blocking layer being composed of a p-type nitride semiconductor including a transition element of group III; and a p-type clad layer formed on the electron blocking layer.

An aluminum-doped zinc oxide (AZO) thin film (200), a preparation method thereof, and a micro electro mechanical system (MEMS) device comprising same. The AZO thin film (200) is formed on a substrate (100), the aluminum dosage concentration of the AZO thin film (200) being increased gradually in the thin film thickness direction; in the preparation method, the AZO thin film (200) is prepared by using a sol-gel method; the MEMS device uses the AZO thin film (200) and form a composite thin film layer (300) on the AZO thin film (200) through chemical vapor deposition filming. The AZO thin film (200) has desirable conductivity, has good lattice matching with the composite thin film layer (300), has matched thermal expansion and low cost, and is nontoxic, pollution free, and simple in preparation.

The invention discloses a double-layer transparent electrode on P type GaN (gallium nitride) in GaN based LED (Light-Emitting Diode). The transparent electrode is composed of a double-layer structure of an ITO (Indium Tin Oxide) film and a ZnO (Zinc Oxide) based film. The process steps are that: 1, the ITO film is deposited on the P type GaN to be used as a first transparent conducting layer, and the thickness is 1-1000 microns; and 2, the low-resistance ZnO based film is deposited on the first transparent conducting layer to be used as a second transparent conducting layer, and the resistivity is 10-4 to 10-5 ohm cm. The double-layer transparent electrode has the advantages of low resistivity, high light transmittance and good stability, the current is uniformly deposited, and the double-layer electrode can improve the luminous efficiency of the GaN based LED and prolong the service life.

The invention discloses a double-sided high temperature super-conductive film multiple-layer structure and the preparation method. The double-sided high temperature super-conductive film multiple-layer structure comprises a non-monomorph oxide uropatagia of low cost, both sides of the non-monomorph oxide uropatagia of low cost are provided with a metal film layer, an oxide film layer of biaxial texture and a super-conductive film layer. At first, the metal film with a good surface is arranged on the non-monomorph oxide uropatagia of low cost and then the ion beam ancillary deposition technology is adopted to prepare the oxide film material of biaxial texture on the metal film, saving the expensive oxide monomorph material as the material of the uropatagia of large area of double-sided high temperature super-conductive film but choosing the Si monomorph of low cost and the like. The double-sided high temperature super-conductive film that is prepared is of low cost.

The invention relates to an inorganic synaptic transistor structure and a manufacturing method thereof. The structure comprises a flexible substrate; a buffer layer formed on the substrate; a bottom gate electrode formed on the buffer layer; an epitaxial gate dielectric layer formed on the bottom gate electrode; a channel layer formed on the epitaxial gate dielectric layer; and a source electrodeand a drain electrode which are disposed on the channel layer. The manufactured synaptic transistor effectively overcomes the defects that the miniaturization and integration of the synaptic transistor adopting ionic liquid or solid electrolyte as a gate medium are difficult to achieve, the linearity and symmetry of a device are worse, and the synaptic transistor is not resistant to high temperature. The synaptic transistor prepared by the method has flexibility, bending resistance and high temperature resistance, the performance can still be kept basically unchanged under the bending condition or at 100 DEG C, and the energy consumption of each device in the learning process is only 10-30 pJ, which is beneficial to the practical application of the synaptic transistor in the field of high-precision artificial neuromorphic calculation.

Provided are a thin film transistor, a method for manufactur thereof and an array substrate. The thin film transistor comprises: a gate electrode (102) formed on a substrate (101), a gate insulating layer (103) formed on the gate electrode (102) and covering at least a part of the substrate (101), and a semiconductor layer (105'), a source electrode (107a) and a drain electrode (107b) formed on the gate insulating layer (103). The material of the semiconductor layer (105') is an oxide semiconductor, and the material of the source electrode (107a) and the drain electrode (107b) is a doped oxide semiconductor. The source electrode (107a), the drain electrode (107b) and the semiconductor layer (105') are disposed in the same layer.

The invention discloses a method for thinning Mg-RE-Mn-Sc series magnesium alloy crystalline grains by adding Zr, which is implemented by adding Mg-Zr intermediate alloy. The method comprises the following steps of: smelting Mg-RE-Mn-Sc magnesium alloy in a corresponding component ratio under the protection of flux or gas, then heating the smelted alloy to between 720 and 740 DEG C, and adding Mg-31wt.%Zr intermediate alloy into the smelted alloy, wherein the adding amount of the Zr accounts for 0.6 to 1.2 weight percent of the total weight of the furnace charge. The method can thin the thick crystalline grains of Mg-RE-Mn-Sc series magnesium alloy and improve the tensile property of the Mg-RE-Mn-Sc series magnesium alloy so as to accelerate the industrialized application progress of the series magnesium alloy.

The invention discloses a GaN device with the mixed polarity. The GaN device relates to the technical field of field effect transistors with two-dimensional carrier gas channels. The GaN device comprises a substrate layer, an N-polar GaN buffer layer, a first N-polar Alx GaN layer with a gradually increased Al component x, a second N-polar AlxGaN layer with a constant Al component x, a third N-polar AlxGaN layer with a gradually reduced Al component x, and a Ga-polar GaN channel layer. By virtue of the structure, a GaN based material with higher quality can grow epitaxially and the surface density and migration rate of 2DEG in a channel can be increased; and meanwhile a device with smaller ohmic contact resistance can be fabricated on a material with the mixed polarity by adopting a conventional Ga-polar GaN based device fabrication process.

The invention discloses a preparation method of a topology insulator/ferromagnet heterostructure film. The preparation method comprises the following steps: (a) N, N-dimethylformamide solution of La0.7Sr0.3MnO3 is prepared; polyvinylpyrrolidone is added in the solution to form a colloid; and the colloid is coated on a substrate for drying, and is put in a tube furnace for insulation annealing treatment to obtain a La0.7Sr0.3MnO3 film; (b) the La0.7Sr0.3MnO3 film is put in a magnetron sputtering instrument; a Bi2Se3 film is deposited on the La0.7Sr0.3MnO3 film through a magnetron sputtering method to obtain a Bi2Se3/La0.7Sr0.3MnO3 heterostructure film; and (c) the Bi2Se3/La0.7Sr0.3MnO3 heterostructure film and selenium particles are sealed in a vacuum quartz tube for post-annealing treatment. The method is simple in operation and low in cost; and the prepared heterostructure film is excellent in performance.