The invention provides a low-resistance silicon on insulator-lateral insulated gate bipolar transistor (SOI-LIGBT) device capable of preventing a snapback effect and a manufacturing method thereof. A cell structure of the low-resistance SOI-LIGBT comprises a substrate, a buried oxide layer, a thick dielectric layer, a thick silicon layer drift region, a P well region, a P-type heavily-doped emitter region, a first N-type heavily-doped region, an N-type buffer region, a P-type heavily-doped collector region, a second N-type heavily-doped region, a collector dielectric blocking layer, a collector contact electrode, an ultrathin top-layer silicon drift region, an emitter contact electrode, a gate oxide layer, a poly-silicon gate, P strips and N strips, wherein the N strips are alternatively arranged in the thick silicon layer drift region in longitudinal directions of the P strips. The electric field of the buried layer is improved by employing the ultrathin top layer silicon drift region to increase the longitudinal breakdown voltage of an SOI device; the specific on resistance of the device is reduced by employing the thick silicon layer drift region; and for the ultrathin top layer silicon drift region and the thick silicon layer drift region, lateral linearity variable doping is used for adjusting surface electric field distribution, so that the specific on resistance is greatly reduced as well as high breakdown voltage of the device is greatly maintained.