The invention discloses a high-performance two-dimensional
transistor and a preparation method and application thereof, and relates to the technical field of
semiconductor material manufacturing, and the structure of the
transistor comprises a channel layer, a
gate dielectric layer and an
electrode assembly. Wherein the channel layer is made of a two-dimensional
semiconductor material; the
gate dielectric layer is made of a layered
phosphorus gallium sulfide material; the
electrode assembly comprises a grid
electrode, a source electrode and a drain electrode; the channel layer and the
gate dielectric layer are combined through
Van der Waals force. The preparation method comprises the following steps: obtaining a two-dimensional material sheet through mechanical stripping, and sequentially stacking the two-dimensional
semiconductor material channel, the layered
phosphorus gallium sulfide dielectric layer and the
graphite grid electrode by adopting a
dry transfer technology. The obtained
transistor shows excellent electrical properties: the current on-off ratio is greater than or equal to 3 * 10 < 8 >, the
gate leakage current is less than or equal to 1 * 10 <-13 > A, the
subthreshold swing is about 85 mV / dec, and the interface
hysteresis voltage is as low as 20 mV. The method is suitable for low-power-consumption and high-performance integrated circuits, logic electronic devices and optoelectronic devices.