57results about How to "Small mismatch" patented technology

The invention relates to a magnetic tunnel junction of a spinel oxide potential barrier, and the application in device thereof. The potential barrier of the magnetic tunnel junction is made of spinel oxides. The tunnel junction may be of a single potential barrier structure or of a double potential barrier structure. The novel single potential barrier magnetic tunnel junction provided by the invention can be applied to a spintronic device and comprises a magneto-dependent sensor, a magnetic random access memory unit, a magnetic logic device unit, a spin transistor and a spin field effect transistor. According to the magnetic tunnel junction based on novel potential barriers, the mismatch degree between a potential barrier layer and a magnetic crystal lattice is quite small, while a high room temperature tunneling magneto-resistor ratio is maintained, the bias dependence feature is quite weak, and the breakdown voltage is improved.

The invention discloses a multilayer homogeneous growth bismuth ferrite thin-film material, including a bottom electrode and a bismuth ferrite thin-film. The bottom electrode is a lanthanum nickelate thin-film, and the bismuth ferrite thin-film is sputtered and grows on the bottom electrode. The invention also discloses a preparation method of the multilayer homogeneous growth bismuth ferrite thin-film material. The method is as below: preparing the bottom electrode by a magnetron sputtering method on a silicon substrate, and preparing the bismuth ferrite thin-film by a solid state method; sputtering a layer of the bismuth ferrite thin film on the bottom electrode, rapidly annealing and repeating the above sputtering process for 6-8 times; and finally, conducting slow annealing treatment to obtain the multilayer homogeneous growth bismuth ferrite thin-film. The bismuth ferrite thin-film obtained by the invention has good uniformity, high purity, good compactness and significantly improved surface properties. The method provided by the invention utilizes magnetron sputtering method, which has strong controllability and is easy for operation and capable of precise control of film thickness.

The invention discloses a frequency doubling self-regulating Q green laser inside a double-doped chrome yttrium aluminum garnet composite photassium titanyl phosphate cavity,and relates to a green laser. The self-regulating Q green laser is provided with a pumping source, a micro lens, a first column-shaped lens, a second column-shaped lens and a laser working medium Cr, Nd:YAG/KTP composite crystal. The pumping source, a micro lens, the first column-shaped lens, the second column-shaped lens and the laser working medium Cr, Nd:YAG/KTP composite crystal sequentially are arrayed on a same plain shaft from front to back. Anti-reflection film and a high-reflective film are plated on the rear surface of the laser working medium Cr, Nd:YAG/KTP composite crystal to serve as a back cavity lens of the laser cavity. High-reflective film and anti-reflection film are plated on the front surface of the laser working medium Cr, Nd:YAG/KTP composite crystal of the laser cavity. The number of optical elements used for the laser is small, the production cost is low, the structure is simple and compact, and the laser is convenient to produce and assemble and operate and use by a non-professional person.

The invention discloses a core-shell quantum dot and a preparation method thereof, wherein the core-shell quantum dot comprises a CdSe core, a CdxZn(1-x)Se shell layer, a ZnSezS(1-z) shell layer, a CdyZn(1-y)S shell layer and a ZnS shell layer, wherein the CdSe core is sequentially coated with the CdxZn(1-x)Se shell layer, the ZnSezS(1-z) shell layer, the CdyZn(1-y)S shell layer and the ZnS shelllayer from inside to outside, x is more than 0 and less than 1, y is more than 0 and less than 1, and z is more than 0 and less than or equal to 1. According to the invention, the core-shell quantum dot has the layer-by-layer progressive energy level structure, is small in the lattice mismatching degree between layers, uniform in the components of the alloy shell, good in size, morphology and monodispersity, narrow in fluorescence half-peak width, high in fluorescence quantum yield, high in stability, simple in whole synthesis process, few in influence factor and good in repeatability.

The invention relates to a material used for a high-dielectric constant (high-k) gate dielectric in a new generation integrated circuit field-effect tube and a preparation method thereof. The epitaxial thin film material used for the high-dielectric constant gate dielectric is a single high-oriented epitaxial thin film on an Si(001) underlay; the thin film is a single-crystalline state hafnium-lanthanum composite oxide La2Hf2O7 with a pyrochlore phase structure; and the crystallographic orientation relationship between the thin film and the Si(001) underlay is La2Hf2O7(001)//Si(001). In the preparation method of the epitaxial thin film, a hafnium-lanthanum composite oxide (La2Hf2O7) ceramic target material with a pyrochlore phase is obtained by a reactive sintering method, and then the single high-oriented epitaxial thin film with smooth surface and even interface is deposited on the Si(001) underlay under the condition of ultrahigh vacuum by adopting a laser molecular beam deposition technology. The epitaxial thin film material is applied to the gate dielectric of the new generation integrated circuit field-effect tube.

This invention relates to dope rare earth element gallium oxide fluorescence substrate material used to GaInN group blue light semiconductor epitaxial growth and its preparation method. The substrate single crystal molecular formula is beta-Ga2-2x(RE)2xO3, the RE equals to Ce or Tm, x equals to 0.001 to 0.1. The crystal grows by floating zone method. The substrate is propitious to epitaxial growth high quality GaInN group blue semiconductor film, LED can emit white light by it combine with GaInN group blue light.

The invention discloses a silicon substrate niobium nitride film superconducting material. The silicon substrate niobium nitride film superconducting material comprises a Si substrate, a TiN transitional layer and an NbN layer. An NbN film is directly arranged on the Si substrate in a growth mode to cause a big lattice mismatch degree so that a non-superconducting interface distortion layer with a certain thickness can exist in the NbN film, and superconducting performance of the NbN film is severely reduced. The TiN transitional layer and the NbN layer are of a face-centred cubic structure, the lattice mismatch degree is small, the TiN transitional layer is used for greatly reducing the interface distortion layer thickness of the NbN film, NbN crystallinity is simultaneously improved, and superconducting performance is improved accordingly. The NbTiN is high-Tc superconducting materials, and even if two elements including Ti and N in the TiN enter the NbN film, the Ti and the N are not reduced, and the superconducting performance of the Ti and the N is improved. The invention further provides a manufacturing method of the silicon substrate niobium nitride film superconducting material.

The invention discloses a large-size doped YIG single crystal thin film material and a preparation method, and belongs to the technical field of thin film materials; the chemical formula of the large-size doped YIG single crystal thin film material is Y3-xAxFe5-yByO12, wherein the A is at least one metal element such as La, Gd, Tb, Dy, Nd and Eu with the ion radius larger than Y ions, and B is atleast one element, such as Al, Ga, Pt, Ge, Si, Zr, Sc, for partial replacement of Fe ion sites. According to the invention, the ferrite single crystal film with the saturation magnetization of 800-1750 Gs and the thickness of more than 20 microns in 3 inches is prepared by a liquid phase epitaxy method, the saturation magnetization range of the film is wider, and the application of the single crystal film in a multi-band microwave device is facilitated; in addition, roughness RMS of the film can be reduced to 0.37 nm, lattice matching with a GGG substrate is good, and production efficiency isremarkably improved.

The invention discloses a quantum dot structure. The quantum dot structure comprises a quantum dot nucleus, a strain compensation layer coating the quantum dot nucleus, and a shell layer coating the strain compensation layer. The lattice matching degree between the quantum dot nucleus and the shell layer or the strain compensation layer is higher than 88%. According to the quantum dot structure provided by the invention, the pressure stress produced by a semiconductor material in the shell layer during growth can be eliminated, and the low stress demand of the quantum dot nucleus can be guaranteed. The invention further provides a manufacturing method of the quantum dot structure, a quantum dot light emitting diode adopting the quantum dot structure, and a manufacturing method of the quantum dot light emitting diode.

The invention relates to a spiral bevel gear tooth surface Ease-off modification design method based on minimum meshing impact. According to the method, a small gear tooth surface completely conjugated with a large gear is derived according to a meshing principle, free Ease-off curved surface design is performed according to an inter-tooth gap and tooth surface normal gap generation principle, andthe free Ease-off curved surface design is superposed with a conjugated tooth surface to represent a small gear modification tooth surface. A spiral bevel gear meshing impact model considering gear tooth loading deformation is established; based on gear tooth TCA and LTCA technologies, the actual meshing point position and rigidity of meshing gear teeth are accurately calculated, the actual meshing point is obtained after a theoretical meshing point position vector of a driven wheel rotates by a small angle under a meshing coordinate system, and the theoretical meshing position is determinedby an intersection point of a geometric transmission error curve and a bearing transmission error curve. The minimum maximum meshing impact force and the minimum tooth surface maximum load are taken as optimization targets to obtain an optimal target modified tooth surface. According to the method, the meshing impact force is reduced while the strength is improved under the small adaptation amount, and a theoretical basis is provided for subsequent spiral bevel gear dynamic analysis.

The invention discloses a base pitch error-considered free modification spiral bevel gear bearing contact analysis method, which comprises the steps of designing a free Ease-off curved surface according to a tooth gap and a tooth surface normal gap generation principle, and superposing the free Ease-off curved surface with a conjugate tooth surface to represent a small gear modification tooth surface; calculating the initial clearance of the tooth surface of a single tooth from an engaging-in contact position to an engaging-out contact position according to a TCA technology; superposing the relative base pitch errors of the simultaneous meshing tooth pairs to the initial clearances of the tooth pairs; completing input data processing of the LTCA method of a certain meshing position in a meshing period, and extracting bearing deformation of the corresponding position in the meshing period and contact position loads of different tooth pairs through LTCA calculation, wherein due to the fact that base pitch errors are unequal, the loads of the different meshing positions of a single tooth need to be obtained through multiple times of cyclic calculation; and finally, applying a machinelearning method (EML) to regression fitting of budget of specific working condition bearing deformation under any random error, and providing a more scientific theoretical basis method for high-performance tooth surface dynamic analysis.

The invention discloses an LED epitaxial growth method. The method sequentially comprises steps of processing a substrate, growing a low-temperature buffer layer GaN, growing an undoped GaN layer, growing a Si-doped N-type GaN layer, growing a multi-quantum well layer, growing an AlGaN electronic blocking layer, growing a Mg-doped P-type GaN layer, performing temperature reduction and cooling, wherein the growth of the multi-quantum well layer sequentially comprises steps of growing a low-temperature GaN barrier layer, growing a pressure gradient InGaN well layer, growing a temperature gradient InGaN well layer, growing a temperature and pressure simultaneous gradient InGaN well layer, growing a high-temperature GaN barrier layer and growing an AlN layer. The method is advantaged in that problems of low quantum well growth quality and low quantum well radiation recombination efficiency in an LED epitaxial growth method in the prior art are solved, so luminous efficiency of an LED is improved, and warping of an epitaxial wafer is reduced.

The composite substrate material of conductive spinel structure MgIn2O4/MgO is constituted via setting one layer of covering MgIn2O4 layer onto the monocrystalline MgO. The preparation process of the composite substrate material includes the first RF magnetically controlled sputtering to prepare In2O3 film on monocrystalline MgO substrate, and the subsequent solid reaction between In2O3 and MgO at high temperature to form covering MgIn2O4 layer on the monocrystalline MgO substrate. The composite substrate material of the present invention has simple preparation process, and MgIn2O4 has small lattice mismatching degree to GaN (111) and is transparent conducting oxide material. The composite MgIn2O4/MgO substrate is suitable for epitaxial growth of high quality GaN.

The invention relates to a preparation method of a cadmium selenide film material, and belongs to the technical field of manufacturing of semiconductors. The preparation method comprises the followingsteps: preparing an InAs film material on a Si substrate; pre-depositing selenium and cadmium on the InAs film material under vacuum condition to obtain a CdSe buffering layer; depositing and growingselenium and cadmium on the CdSe buffering layer; and cooling to obtain a cadmium selenide film. The method for growing an II-VI group film on the III-V group substrate material is simple, small in requirements on instruments and equipment, low in cost, and easy to operate; and the cadmium selenide film prepared by the method is flat and uniform in surface.

The invention discloses an LED epitaxial growth method based on graphene. The method sequentially comprises the following steps: growing a high-temperature gradient graphene layer, an n-type heavily-doped AlN layer, a low-temperature gradient graphene layer, an n-type lightly-doped AlN layer, a Si-doped N-type GaN layer, a periodically-grown MQW active layer, a P-type AlGaN layer and a Mg-doped P-type GaN layer on a sapphire substrate, and cooling. According to the method, the high-temperature gradient graphene layer, the n-type heavily-doped AlN layer, the low-temperature gradient graphene layer and the n-type lightly-doped AlN layer are adopted, so that warping of the LED epitaxial wafer can be reduced, the quality of epitaxial crystals is improved, and the photoelectric performance of an LED is improved.

A compound substrate material suitable for InN-GaN epitaxial growth is to set a layer of MgIn2O4 o MgO single crystal. The preparation method is to put mixed ingots of MgIn2O4 and In2o3 with gas holes in a Pt pot, put or hang a MgO wafer of double or single polish on Pt silk added by a Pt plates covered by mixed powders of MgIn2O4 and In2O3 and cover the pot closely by a Pt cover then put it in a resistance furnace, heating up to 800~1400deg.c. kept constant for 20~100h, the In2O3 is reacted with MgO in solid phase by In3+ ionic diffusion to get the said material.

The invention discloses a GaN-based LED structure, which sequentially comprises a substrate, a first N-type doped GaN layer, a first ZnGeN2 barrier layer, a second N-type doped GaN layer, a multi-quantum well layer and a P-type doped GaN layer from bottom to top. The invention also discloses a preparation method of the GaN-based LED structure.

The invention provides a multi-junction solar cell and power supply equipment. In at least one sub-cell, the average lattice constant of a sub-cell window layer is greater than a first lattice constant, and the mismatch degree of the average lattice constant of the sub-cell window layer and the first lattice constant is less than 1%. Therefore, the sub-cell window layer is made of a material whichis in lattice mismatch with the active region of the sub-cell so that the band gap of the sub-cell window layer is increased, sunlight absorption of the sub-cell window layer is reduced, a high potential barrier is formed, a reflection effect on minority carriers flowing to the sub-cell window layer is achieved, the collection efficiency of photon-generated carriers is finally improved and the performance of the multi-junction solar cell is improved.

The invention provides a band-gap reference voltage source circuit. The band-gap reference voltage source circuit comprises an operation amplifier, a third resistor, a first node, a second node, a sampling switch, a first capacitor, a filter, a switch combination circuit, N bipolar transistors, a second resistor, a first MOS transistor and a second MOS transistor. The first input end of the operation amplifier is connected with the second middle node, the second input end of the operation amplifier is connected with the first node through the third resistor, and the output end of the operationamplifier is grounded after passing through the sampling switch and the first capacitor in sequence. The first connecting ends of all the bipolar transistors are connected with the switch combinationcircuit, the second connecting ends of all the bipolar transistors are connected with the control ends of the bipolar transistors themselves and are grounded, and the switch combination circuit makesthe first connecting ends of all the bipolar transistors selectively connected with the first node or the second node. Compared with the prior art, the band-gap reference voltage source circuit can further improve the precision of output reference voltage.

MgIn2O4 covers MgAl2O4 monocrystal constitutes composite substrate material. Method for preparing the said material includes following steps: MgIn2O4 covering layer is formed on substrate of MgAl2O4 monocrystal through deposition process by using pulsed laser. Then, through high temperature annealing, crystallized MgIn2O4 film is obtained on substrate of MgAl2O4 monocrystal. The method possesses features of simple technique and easy of implementation. The composite MgIn2O4 / MgAl2O4 substrate is suitable to epitaxial growth of GaN in high quality.

The invention discloses a method for preparing a polycrystalline silicon thin film by amorphous silicon low-temperature induction, belonging to the technical field of thin-film solar battery. The method overcomes the disadvantage of slow crystallization rate of the existing metal induction method. According to the invention, a titanium silicide nano-wire layer and an amorphous silicon thin film layer are sequentially deposited on a substrate from bottom to top, wherein the titanium silicide nano-wire layer induces the amorphous silicon thin film layer to form a polycrystalline silicon thin film layer, thereby forming a polycrystalline silicon thin film having a three-layer composite structure consisting of the substrate, a transition layer with coexisting titanium silicide nano-wire and polycrystalline silicon thin film, and the polycrystalline silicon thin film layer. On one hand, the crystallization of the amorphous silicon thin film can be induced at a lower crystallization temperature easily since the titanium silicide nano-wire is used as an inducer; on the other hand, the titanium silicide nano-wire with a huge specific surface area can increase the contact area between the induction layer and the amorphous silicon, thereby increasing the nucleation number in the initial crystallization stage of the amorphous silicon and greatly improving the crystallization rate; and the entire crystallization process is completed in 2 to 4 hours.