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89results about How to "Increase the bandgap width" patented technology

Vertical gallium nitride based nitride heterojunction field effect transistor with polarized doped current barrier layer

The invention provides a vertical gallium nitride based nitride heterojunction field effect transistor with a polarized doped current barrier layer, which sequentially and mainly comprises a drain electrode, an n<+>-GaN substrate, an n-GaN buffer layer, a GaN channel layer, an AlGaN barrier layer, a source electrode on the AlGaN barrier layer and a grid electrode on the AlGaN barrier layer from bottom to top, wherein the source electrode and the drain electrode are both in ohmic contact, the grid electrode is in Schottky contact, the vertical gallium nitride based nitride heterojunction field effect transistor further comprises the polarized doped p-AlGaN current barrier layer between the n-GaN buffer layer and the GaN channel layer, and an Al component in the current barrier layer increases gradually in the y direction. According to the vertical gallium nitride based nitride heterojunction field effect transistor with the polarized doped current barrier layer, a polarized electric field, produced by the gradual change of the Al component in the current barrier layer, increases the activation rate of p-type impurities and the hole concentration of the current barrier layer, so that the breakdown voltage of an element is increased.
Owner:UNIV OF ELECTRONICS SCI & TECH OF CHINA

Method for preparing silicon heterojunction solar cell containing composite emission layer

The invention provides a method for preparing a silicon heterojunction solar cell containing a composite emission layer. The method includes the steps that an amorphous silicon back field N is deposited on one face of a substrate C on which a double-faced intrinsic amorphous silicon passivation layer I is deposited, an amorphous silicon layer P2 with the uniform structure is prepared on the face opposite to the amorphous silicon back field N under the conditions that doping concentration, hydrogen dilution and power density are low, a nanocrystalline silicon layer P1 with the uniform structure is prepared under the conditions that the doping concentration, the hydrogen dilution and the power density are improved, and an amorphous silicon / nanocrystalline silicon composite structure formed by the two silicon films serves as the emission layer of the silicon heterojunction solar cell. Materials have the advantages of being high in transmittance and conductivity through the structure, on the basis, the passivation effect of the surface of crystalline silicon can be improved, short wave response and output characteristics of the cell are improved, and the method for preparing the silicon heterojunction solar cell is simple and easy to carry out.
Owner:捷造科技(宁波)有限公司

Gallium nitride power device with multi-field plate structure, and preparation method thereof

The invention discloses a gallium nitride power device with a multi-field plate structure. The gallium nitride power device is sequentially provided with a substrate, a nucleating layer, a buffer layer, a first insertion layer, a first GaN layer, a second insertion layer, a second GaN layer, an AlGaN barrier layer, a passivation layer, a grid electrode field plate, a drain electrode field plate, aprotective layer, a grid electrode insertion layer, a p-type GaN grid electrode, a grid electrode metal, a source electrode metal and a drain electrode metal from bottom to top, wherein the passivation layer located on the surface of the AlGaN barrier layer is in a strip shape arranged at intervals, the grid electrode field plate and the drain electrode field plate respectively cover part of thepassivation layer, and the surfaces of the grid electrode field plate and the drain electrode field plate and the space between the grid electrode field plate and the drain electrode field plate are covered with the protective layer. According to the invention, the electric field distribution is uniform, the voltage endurance capability of the device is enhanced, the stability of grid electrode turn-on voltage and grid electrode voltage of the device is effectively improved, and the electric leakage of the device under the action of large current is effectively reduced. The preparation methodis completely compatible with a traditional process, and the preparation difficulty is low.
Owner:CHANGSHU INSTITUTE OF TECHNOLOGY

Film solar battery based on crystalline silicon and formation method thereof

The invention relates to a film solar battery based on crystalline silicon and a formation method thereof. The battery comprises a baseplate made of monocrystalline silicon or polysilicon, a photoelectric conversion unit positioned on the upper surface of the baseplate, an antireflection layer, a front electrode and a back electrode, wherein the photoelectric conversion unit successively comprises a P-type semiconductor layer, an I-type semiconductor layer and an N-type semiconductor layer,; the P-type semiconductor layer comprises multiple P-type semiconductor sublayers with different doped ion concentrations, and the P-type semiconductor sublayers are successively arranged in a stacking manner according to the doped ion concentrations; the N-type semiconductor layer comprises multiple N-type semiconductor sublayers with different doped ion concentrations, and the N-type semiconductor sublayers are successively arranged in a stacking manner according to the doped ion concentrations; the doped ion concentrations of the P-type semiconductor sublayer and the N-type semiconductor sublayer which are positioned on the surface of the I-type semiconductor layer are minimal; and the antireflection layer is positioned on the upper surface of the photoelectric conversion unit, the front electrode is positioned on the upper surface of the antireflection layer, and the back electrode is positioned on the lower surface of the baseplate. According to the invention, the photoelectric conversion efficiency can be improved.
Owner:SILEVO CHINA

Method of preparing n-type counterfeit ternary erbium-doped thermoelectric material by utilizing mechanical alloying cold pressing sintering method

The invention discloses a method of preparing an n-type counterfeit ternary erbium-doped thermoelectric material by utilizing a mechanical alloying cold pressing sintering method, and relates to a method of preparing a thermoelectric material. The invention solves the technical problems of easiness in separation, poor mechanical property and high material cost of the conventional thermoelectric material. The method comprises the following steps of: 1, mixing a simple substance Bi, a simple substance Sb, a simple substance Te and a simple substance Se, adding a rare earth element Er, and ball-milling to obtain alloy powder; 2, cold-pressing the alloy powder to a block at room temperature; 3, placing the cold-pressing block obtained in the step 2 into a high-temperature-resistant glass tube, sintering, and cooling to room temperature along with a furnace so as to obtain the n-type counterfeit ternary erbium-doped thermoelectric material. The material, prepared by the method in the invention, has a thermoelectromotive force rate close to an oriented crystal, according to the national departmental standard, the Seebeck coefficient of the material is tested to reach 200 muVK<-1>, the conductivity is 55 omega<-1>cm<-1>, and a power factor is close to 2 muWcm<-1>K<-2>.
Owner:HARBIN NORMAL UNIVERSITY

Bismuth oxybromide ternary heterostructure photocatalyst as well as preparation method and application thereof

The invention discloses a preparation method of a bismuth oxybromide ternary heterostructure photocatalyst. The method uses bismuth nitrate pentahydrate, potassium bromide, graphite phase carbon nitride and silver nitrate as raw materials; the prepared graphite phase carbon nitride and silver bromide are compounded with bismuth oxybromide so as to realize modification; the bismuth oxybromide ternary heterostructure photocatalyst is prepared by using a one-step solvothermal method. The modified bismuth oxybromide prepared by the method is purer, has a smaller forbidden band width and a higher visible light absorbing effect. The smaller forbidden band width reduces the transmission distance of photogenerated electron holes, improves the separation efficiency of the photogenerated electron holes, and reduces the recombination rate; the higher light absorption effect improves photon utilization rate, increases the yield of the electron hole pairs, and greatly improves the photocatalytic activity under the visible light. The method has the advantages of being low in cost and convenient to operate; the bismuth oxybromide ternary heterostructure photocatalyst can be used for degrading organic pollutants under the visible light, thus having an important practical value in environmental purification.
Owner:LIAONING UNIVERSITY

Preparation method of high k-gate dielectric layer and silicon carbide MOS power device

The present invention provides a preparation method of a high k-gate dielectric layer and a silicon carbide MOS power device. The preparation method comprises the steps of: performing high-temperaturesacrificial oxidation of a silicon carbide epitaxial wafer with a first conductive type, and forming a sacrificial oxidation layer at the upper surface of the epitaxial layer of the silicon carbide epitaxial wafer; performing corrosion of the sacrificial oxidation layer until the sacrificial oxidation layer on the epitaxial layer is completely removed; performing high-temperature surfacing processing of the upper surface of the epitaxial layer after removal of the sacrificial oxidation layer, and forming a smooth passivated surface; and depositing an Al2O3 dielectric coating layer, a LaAlO3 dielectric layer and an Al2O3 dielectric coating layer at the smooth passivated surface in order, performing annealing of a laminated structure formed by the Al2O3 dielectric coating layer, the LaAlO3dielectric layer and the Al2O3 dielectric coating layer, and forming a high k-gate dielectric layer. Compared to the prior art, the preparation method of the high k-gate dielectric layer and the silicon carbide MOS power device can reduce the interface defects caused by impurities and/or surface lattice defects at a SiC/SiO2 interface so as to improve the voltage endurance capability of the gate dielectric layer.
Owner:GLOBAL ENERGY INTERCONNECTION RES INST CO LTD +2

Thin film solar battery and manufacturing method thereof

The invention relates to a thin film solar battery and a manufacturing method thereof. The thin film solar battery comprises a substrate, a first I-type semiconductor layer, a P-type semiconductor layer and a first electrode, a second I-type semiconductor layer, an N-type semiconductor layer and a second electrode, wherein the first I-type semiconductor layer, the P-type semiconductor layer and the first electrode are positioned at one side of the substrate in sequence, and the concentration of ions doped in the P-type semiconductor layer successively increases from the direction adjacent to the first I-type semiconductor layer to the direction far away from the first I-type semiconductor layer; the second I-type semiconductor layer, the N-type semiconductor layer and the second electrode are positioned at the other side of the substrate in sequence, and the concentration of ions doped in the N-type semiconductor layer successively increases from the direction adjacent to the second I-type semiconductor layer to the direction far away from the second I-type semiconductor layer. The invention has the beneficial effect that not only can the pollution of the P-type semiconductor layers or the N-type semiconductor layers to the I-type semiconductor layers be reduced, but also the larger band gap width can be obtained, and therefore, the photoelectric conversion efficiency is high.
Owner:SILEVO CHINA

Flexible composite laminated solar cell and preparation method thereof

The invention discloses a flexible composite laminated solar cell and a preparation method thereof. The composite laminated solar cell sequentially comprises a high-wear-resistance light-transmittinglayer, a charge transmission layer, a perovskite cell layer, a hole transmission layer, a gallium arsenide cell layer, a metal electrode layer and a flexible packaging backboard layer from a light receiving surface to a backlight surface. The structure is a thin-layer flexible structure and can be bent, curled and folded; according to the invention, the problems of gallium arsenide energy loss andlattice mismatch are solved, the energy gap is large, the overall conversion efficiency is improved, and the service life is prolonged. According to the invention, the charge transport layer is prepared by adopting a spraying method, the hole transmission layer is prepared by adopting a spray pyrolysis method, the metal electrode layer is prepared by adopting a coating method, and the flexible packaging backboard layer is prepared by adopting a thermal bonding method; the preparation difficulty is reduced while the thin layer preparation requirement is met, industrial popularization is facilitated, layer-to-layer combination is facilitated through selection of the preparation method, and then the conversion efficiency is improved.
Owner:兴储世纪科技股份有限公司

Thin film solar cell and formation method thereof

The invention relates to a thin film solar cell and a formation method thereof. The thin film solar cell comprises a substrate, a photoelectric conversion unit, an anti-reflective layer, a positive electrode, and a backplate. The photoelectric conversion unit, which is arranged on the upper surface of the substrate, includes a P type semiconductor layer, an I type semiconductor layer, and an N type semiconductor layer; doped ion concentration in the P type semiconductor layer is successively increased along a direction from a position close to the I type semiconductor layer to a position far from the I type semiconductor layer; and doped ion concentration in the N type semiconductor layer is successively increased along a direction from a position close to the I type semiconductor layer to a position far from the I type semiconductor layer. Besides, the anti-reflective layer is arranged on the upper surface of the photoelectric conversion unit; the positive electrode is arranged on the upper surface of the anti-reflective layer; and the backplate is arranged on the lower surface of the substrate. According to the invention, pollution on an I type semiconductor layer by a P type semiconductor layer or an N type semiconductor layer can be reduced; and a broad band gap can be realized; therefore, photoelectric conversion efficiency is high.
Owner:SILEVO CHINA

Method for preparing wide bandgap nanometer cadmium sulfide thin film

The invention relates to a method for preparing a wide bandgap nanometer cadmium sulfide thin film, which comprises the following steps that: indium tin oxide (ITO) glass using as substrates is placed in a reaction container after organic solvent soaking, ultrasonic cleaning and drying, and oxidbillity additives are added into reaction solution; in the reaction solution preparation stage, cadmiumsalt and the same acid radical ammonium salt are added into the container, de-ionized water is then added, when the temperature is heated to 40 to 70 DEG C, the proper amount of weak base aqueous solution (ammonia solution) is added for producing cadmium complex compounds, and the reaction solution in the first step is formed; and the weak base solution is added, simultaneously, the oxidbillity additives are added, the additives are organic peroxide (ROOH), organic peroxyacetic acid (RCOOOH) and 2 percent to 30 percent of oxyful, and the addition quantity of the oxidbillity additives is 1 percent to 10 percent of the mol number of the cadmium salt. At the time, thiourea is then added, the light transmittance and the energy gap of the wide bandgap nanometer cadmium sulfide thin film are obviously improved, and window materials of copper indium gallium selenium batteries or cadmium telluride batteries can be more favorably manufactured.
Owner:NANJING UNIV

Mid-far infrared avalanche photodetector

The invention discloses a mid-far infrared avalanche photodetector which comprises a substrate, a buffer layer, a lower ohmic contact layer, a multiplication layer, a charge layer, a gradient layer, an absorption layer and an upper ohmic contact layer which are sequentially connected from bottom to top, and the doping type of the substrate and the buffer layer is n type. Or the mid-far infrared avalanche photodetector comprises the substrate, the buffer layer, a second ohmic contact layer, the absorption layer, the gradient layer, the charge layer, the multiplication layer and a first ohmic contact layer which are sequentially connected from bottom to top, and the doping type of the substrate and the buffer layer is p type, wherein the multiplication layer is made of an AlAsxSb1-x material, x is greater than or equal to 0.12 and less than or equal to 0.18, the gradient layer is of a plurality of (InAs)m/(AlAs0.15Sb0.85)n quantum well structures or an InyAl1-yAszSb1-z material, and thedetection wavelength of the absorption layer is a middle and far infrared band. The mid-far infrared avalanche photodetector provided by the invention can block dark current and reduce noise, does notneed a cooling device, improves the working temperature of the device, reduces the cost, and is convenient to use.
Owner:INST OF SEMICONDUCTORS - CHINESE ACAD OF SCI

VCSEL chip with high recombination efficiency and manufacturing method thereof

The invention relates to the technical field of laser chips, in particular to a VCSEL chip with high recombination efficiency and a manufacturing method thereof. The VCSEL chip comprises a substrate,an epitaxial layer and an N-contact, the epitaxial layer comprises an N-DBR, a quantum well, an oxide layer and a P-DBR, the P-DBR, the oxide layer and the quantum well are etched to the surface of the N-DBR to form a table top, the quantum well comprises a plurality of pairs of quantum well composite layers, each quantum well composite layer comprises AlxGaAs potential barriers, InGaAs potentialwells and AlxGaAs potential barriers which are grown in an overlapping mode, the P-DBR is divided into a central area, a middle area and an edge area, the central area is a light outlet hole, a firstSiNx layer grows on the P-DBR at the position corresponding to the central area, a P-contact is evaporated on the P-DBR at the position corresponding to the middle area, and a second SiNx layer growson the P-DBR at the position corresponding to the edge area. The potential barrier in the quantum well in the VCSEL chip has high forbidden bandwidth, lattice matching is easy to achieve, more electrons are intensively bound in the quantum well, excitation probability is increased, composite efficiency is improved, and therefore, stimulated radiation with higher efficiency is achieved.
Owner:威科赛乐微电子股份有限公司

Two-dimensional photonic crystal of linear gradually-changed structure

A two-dimensional photonic crystal of a linear gradually-changed structure comprises a matrix made of a low-dielectric-constant material, and high-dielectric-constant material columns are embedded into the material of the matrix and distributed in a square in space periodically. The radiuses of the columns are linearly and gradually increased or reduced in the wave propagation direction at a certain step length, the radiuses of the columns are not changed in the direction perpendicular to the wave propagation direction, and the center distances of the columns in the two directions are lattice constants. By optimizing structural parameters, under the condition that the dielectric ratio is relatively low, the relative band gap width is nearly 200% that of a standard square structure; under the condition that the dielectric ratio is higher, the band gap width is 2-5 times that of the standard structure. Compared with a traditional structure, the band gap rate is greatly increased. Compared with other complex structures, design is simple, a user can select a required forbidden band range according to materials needing to be adjusted and the structural parameters, and important value is provided for design, manufacturing and application of the two-dimensional photonic crystal.
Owner:XIDIAN UNIV

Thin-film transistor and manufacturing method thereof, array substrate and display device

The invention provides a manufacturing method of a thin-film transistor. The method comprises a step of deposition of an amorphous silicon layer; a step of formation of a polycrystalline silicon layer through crystallizing treatment; a step of formation of an active layer; a step of formation of channel doping; a step of carbon ion injection; a step of formation of via holes; a step of formation of a gate electrode insulating layer and a gate electrode; and a step of formation of a source electrode and a drain electrode. According to the manufacturing method of the thin-film transistor, forbidden bandwidth of the active layer can be enhanced and thus leakage current of a low-temperature polycrystalline silicon thin-film transistor can be reduced. Besides, visible light absorption coefficient of low-temperature polycrystalline silicon can also be reduced, and light-induced leakage current generated by a backlight source can be reduced. Furthermore, the manufacturing method of the thin-film transistor is suitable for existing polycrystalline silicon thin-film transistor production lines without additional number of times of photo-masking or modification of production equipment, and thus the operation method is easy and convenient. The invention also provides the thin-film transistor, an array substrate and a display device.
Owner:TRULY HUIZHOU SMART DISPLAY

Heterojunction spinning field effect transistor based on 4H-SiC substrate, and manufacturing method for heterojunction spinning field effect transistor

The invention relates to a heterojunction spinning field effect transistor based on a 4H-SiC substrate, and a manufacturing method for the heterojunction spinning field effect transistor. The method comprises the following steps: selecting the 4H-SiC substrate; growing a Ga2O3 epitaxial layer on the surface of the 4H-SiC substrate through employing the MBE technology; forming a source region and a drain region on the Ga2O3 epitaxial layer through the ion implantation technology; respectively forming a source region ohmic contact electrode and a drain region ohmic contact electrode in the resource region and the drain region; growing an oxidation layer on the Ga2O3 epitaxial layer, and carrying out the etching to form a grid region; forming a Schottky contact grid electrode on the surface of the grid region through the technology of magnetron sputtering, and finally forming the heterojunction spinning field effect transistor based on the4H-SiC substrate. According to the invention, the source and drain regions are formed in a mode of selecting regions and carrying out the implantation of Fe ions. The method is compatible with the conventional technology, is simple in manufacturing, is small in surface effect, and can improve the spinning injection and receiving efficiency.
Owner:XIDIAN UNIV

Preparation method and purpose of top cell P type layer of amorphous silicon germanium thin-film solar cell

The invention discloses a preparation method and purpose of a top cell P type layer of an amorphous silicon germanium thin-film solar cell. According to the method, a P type layer of a top cell is prepared by a radio frequency plasma enhanced chemical vapor deposition (RF-PECVD) method; and reactant gas includes hydrogen, silane, and borane. During deposition, gas flow volume proportion of the hydrogen to silane to borane is maintained to be 150 to 200 : 1 : 3 to 8; the borane is borane- hydrogen mixed gas, wherein the borane volume concentration is 0.5%; the air pressure is 160 to 220 Pa; the preparation temperature is within 100 DEG C; the power density inside the cavity is over 300mW / cm<2>; and the band gap width of the P type layer is over 2.0 eV. With the P type layer, the top cell can obtain the high open-circuit voltage and the short-circuit current density can be reduced properly and thus the short-circuit currents generated by the top cells in all sub cells of dual-junction and three-junction cells are the lowest ones, thereby forming a top cell current limitation effect. Therefore, current matching among all sub cells and the fill factors of the integrated cells can be effectively improved, thereby improving the photoelectric conversion efficiency of the dual-junction and three-junction amorphous silicon germanium thin-film solar cells.
Owner:SHANGHAI INST OF SPACE POWER SOURCES
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