This invention discloses a
silicon-based RC
chip co-packaging structure for power devices and its fabrication method. The co-packaging structure includes, from bottom to top, a heat dissipation substrate, a common substrate, a power
chip, a
silicon-based RC buffer
chip, an interconnect structure, power terminals, and auxiliary terminals. The fabrication method includes the following process flows: S100 substrate fabrication, S200 chip mounting, S300 interconnect
assembly, and S400 substrate and terminal
assembly. This invention achieves high compatibility with existing
power module packaging processes, eliminating the need for additional dedicated equipment or significant
production line modifications. While reducing manufacturing costs, improving production yield, and shortening production cycles, it ensures consistent performance in
mass production through standardized processes. Overall, this invention optimizes parasitic parameters, achieves compact structure, integrates thermal management, and stabilizes performance in power modules, making it suitable for various high-
voltage, high-frequency, and high-power-density
power electronics applications.